/arch/s390/lib/ |
H A D | div64.c | 19 register uint32_t reg2 asm("2"); 34 reg2 = 0UL; 38 : "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" ); 64 : "+d" (reg2), "+d" (reg3), "=d" (tmp) 67 return reg2; 129 register uint32_t reg2 asm("2"); 133 reg2 = 0UL; 137 : "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" ); 142 : "+d" (reg2), "+d" (reg3) : "d" (base) : "cc" ); 144 return reg2; [all...] |
/arch/arm/lib/ |
H A D | csumpartialcopy.S | 32 .macro load2b, reg1, reg2 34 ldrb \reg2, [r0], #1 41 .macro load2l, reg1, reg2 43 ldr \reg2, [r0], #4 46 .macro load4l, reg1, reg2, reg3, reg4 47 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
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H A D | memcpy.S | 23 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort 24 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} 27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} 39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} 47 .macro enter reg1 reg2 48 stmdb sp!, {r0, \reg1, \reg2} 51 .macro exit reg1 reg2 52 ldmfd sp!, {r0, \reg1, \reg2} [all...] |
H A D | copy_from_user.S | 47 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort 49 ldr1w \ptr, \reg2, \abort 54 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 55 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort 67 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 68 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} 75 .macro enter reg1 reg2 77 stmdb sp!, {r0, r2, r3, \reg1, \reg2} 80 .macro exit reg1 reg2 82 ldmfd sp!, {r0, \reg1, \reg2} [all...] |
H A D | copy_to_user.S | 47 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort 48 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} 51 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 52 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} 63 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 65 str1w \ptr, \reg2, \abort 78 .macro enter reg1 reg2 80 stmdb sp!, {r0, r2, r3, \reg1, \reg2} 83 .macro exit reg1 reg2 85 ldmfd sp!, {r0, \reg1, \reg2} [all...] |
H A D | csumpartialcopyuser.S | 32 .macro load2b, reg1, reg2 34 ldrusr \reg2, r0, 1 41 .macro load2l, reg1, reg2 43 ldrusr \reg2, r0, 4 46 .macro load4l, reg1, reg2, reg3, reg4 48 ldrusr \reg2, r0, 4
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/arch/arm/kernel/ |
H A D | hyp-stub.S | 40 .macro store_primary_cpu_mode reg1, reg2, reg3 43 adr \reg2, .L__boot_cpu_mode_offset 44 ldr \reg3, [\reg2] 45 str \reg1, [\reg2, \reg3] 54 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 55 adr \reg2, .L__boot_cpu_mode_offset 56 ldr \reg3, [\reg2] 57 ldr \reg1, [\reg2, \reg3] 60 strne \reg1, [\reg2, \reg3] @ record what happened and give up 65 .macro store_primary_cpu_mode reg1:req, reg2 [all...] |
H A D | kprobes-test.h | 234 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ 235 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ 237 TEST_ARG_REG(reg2, val2) \ 239 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ 242 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ 243 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ 245 TEST_ARG_REG(reg2, val2) \ 248 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ 251 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ 252 TESTCASE_START(code1 #reg1 code2 #reg2 code [all...] |
/arch/unicore32/lib/ |
H A D | copy_from_user.S | 40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort 41 100: ldm.w (\reg1, \reg2, \reg3, \reg4), [\ptr]+ 48 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 49 100: ldm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+ 64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 65 stm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+
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H A D | copy_to_user.S | 40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort 41 ldm.w (\reg1, \reg2, \reg3, \reg4), [\ptr]+ 44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 45 ldm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+ 57 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 58 100: stm.w (\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8), [\ptr]+
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/arch/s390/kernel/ |
H A D | cpcmd.c | 26 register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf; 37 : "+d" (reg3) : "d" (reg2) : "cc"); 43 register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf; 62 : "d" (reg2), "d" (reg3), "d" (*rlen) : "cc");
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/arch/x86/kernel/cpu/ |
H A D | perf_event_intel_uncore_nhmex.c | 347 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local 366 reg2->config = event->attr.config2; 374 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local 378 wrmsrl(reg1->reg + 1, reg2->config); 438 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local 451 reg2->config = event->attr.config2; 459 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local 464 wrmsrl(reg1->reg + 2, reg2->config); 665 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; local 686 if (reg2 734 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; local 762 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; local 832 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local 975 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local 1083 struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; local 1108 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; local [all...] |
/arch/powerpc/kernel/ |
H A D | kvm_emul.S | 30 #define LL64(reg, offs, reg2) ld reg, (offs)(reg2) 31 #define STL64(reg, offs, reg2) std reg, (offs)(reg2) 33 #define LL64(reg, offs, reg2) lwz reg, (offs + 4)(reg2) 34 #define STL64(reg, offs, reg2) stw reg, (offs + 4)(reg2)
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/arch/score/include/asm/ |
H A D | processor.h | 51 unsigned long reg0, reg2, reg3; member in struct:thread_struct 81 .reg2 = 0, \
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/arch/s390/include/asm/ |
H A D | tlbflush.h | 47 register unsigned long reg2 asm("2"); 60 reg2 = reg3 = 0; 64 : : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
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H A D | page.h | 43 register void *reg2 asm ("2") = page; 47 : "+d" (reg2), "+d" (reg3) : "d" (reg1) 58 register void *reg2 asm ("2") = to; 64 : "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5)
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H A D | checksum.h | 31 register unsigned long reg2 asm("2") = (unsigned long) buff; 37 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
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/arch/m32r/kernel/ |
H A D | align.c | 277 int reg1, reg2; local 280 reg2 = get_reg(regs, REG2(insn)); 284 : "+r" (reg1) : "r" (reg2) 294 int reg1, reg2; local 297 reg2 = get_reg(regs, REG2(insn)); 303 : "+r" (reg1), "+r" (reg2) 307 regs->acc0l = reg2; 314 int reg1, reg2; local 317 reg2 = get_reg(regs, REG2(insn)); 323 : "+r" (reg1), "+r" (reg2) [all...] |
H A D | ptrace.c | 225 unsigned long reg1, reg2; local 227 reg2 = get_stack_long(child, reg_offset[regno2]); 232 return reg1 == reg2; 235 return reg1 != reg2; 237 return reg2 == 0; 239 return reg2 != 0; 241 return (int)reg2 < 0; 243 return (int)reg2 >= 0; 245 return (int)reg2 <= 0; 247 return (int)reg2 > [all...] |
/arch/x86/kernel/ |
H A D | uprobes.c | 281 u8 reg2; local 354 reg2 = 0xff; /* Fetch vex.vvvv */ 356 reg2 = insn->vex_prefix.bytes[1]; 358 reg2 = insn->vex_prefix.bytes[2]; 366 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7; 373 if (reg != 6 && reg2 != 6) { 374 reg2 = 6; 376 } else if (reg != 7 && reg2 != 7) { 377 reg2 [all...] |
/arch/s390/kvm/ |
H A D | priv.c | 201 int reg2; local 206 kvm_s390_get_regs_rre(vcpu, NULL, ®2); 207 addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; 597 int reg1, reg2; local 599 kvm_s390_get_regs_rre(vcpu, ®1, ®2); 604 if (reg2) { 605 vcpu->run->s.regs.gprs[reg2] &= 0xffffffff00000000UL; 606 vcpu->run->s.regs.gprs[reg2] |= 624 int reg1, reg2; local 629 kvm_s390_get_regs_rre(vcpu, ®1, ®2); [all...] |
H A D | intercept.c | 293 int reg1, reg2, rc; local 295 kvm_s390_get_regs_rre(vcpu, ®1, ®2); 298 srcaddr = kvm_s390_real_to_abs(vcpu, vcpu->run->s.regs.gprs[reg2]);
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/arch/xtensa/lib/ |
H A D | memset.S | 33 #define EX(insn,reg1,reg2,offset,handler) \ 34 9: insn reg1, reg2, offset; \
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H A D | strnlen_user.S | 18 #define EX(insn,reg1,reg2,offset,handler) \ 19 9: insn reg1, reg2, offset; \
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/arch/arm64/kernel/ |
H A D | insn.c | 567 enum aarch64_insn_register reg2, 617 reg2); 907 enum aarch64_insn_register reg2, 944 reg2); 566 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, enum aarch64_insn_register reg2, enum aarch64_insn_register base, int offset, enum aarch64_insn_variant variant, enum aarch64_insn_ldst_type type) argument 904 aarch64_insn_gen_data3(enum aarch64_insn_register dst, enum aarch64_insn_register src, enum aarch64_insn_register reg1, enum aarch64_insn_register reg2, enum aarch64_insn_variant variant, enum aarch64_insn_data3_type type) argument
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