| /drivers/staging/vt6655/ |
| H A D | hostap.h | 44 #define WLAN_RATE_48M BIT10
|
| H A D | 80211hdr.h | 47 #define BIT10 0x00000400 macro
163 #define WLAN_GET_FC_MOREFRAG(n) ((((unsigned short)(n) << 8) & (BIT10)) >> 10)
184 #define WLAN_GET_CAP_INFO_SHORTSLOTTIME(n) ((((n)) & BIT10) >> 10)
196 #define WLAN_GET_FC_MOREFRAG(n) ((((unsigned short)(n)) & (BIT10)) >> 10)
217 #define WLAN_GET_CAP_INFO_SHORTSLOTTIME(n) (((n) & BIT10) >> 10)
|
| /drivers/net/wireless/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 58 #define BIT10 0x00000400 macro
|
| /drivers/staging/emxx_udc/ |
| H A D | emxx_udc.h | 97 #define BIT10 0x00000400 macro
130 #define INT_SEL BIT10
189 #define EP2_INT BIT10
216 #define EP2_EN BIT10
257 #define EP0_IN_DATA BIT10
310 #define EPn_OPIDCLR BIT10
342 #define EPn_IPID BIT10 /* R */
373 #define EPn_DEND_SET BIT10
|
| /drivers/staging/rtl8188eu/hal/ |
| H A D | odm_RTL8188E.c | 42 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);
74 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);
90 BIT10|BIT9|BIT8, 1);
130 phy_set_bb_reg(adapter, 0x864, BIT10, 0);
138 phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1);
146 phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0);
|
| H A D | phy.c | 1226 phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
1228 phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
1229 phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
|
| /drivers/staging/rtl8188eu/include/ |
| H A D | odm_debug.h | 70 #define ODM_COMP_PATH_DIV BIT10
|
| H A D | osdep_service.h | 117 #define BIT10 0x00000400 macro
|
| H A D | rtl8188e_spec.h | 36 #define BIT10 0x00000400 macro
561 #define RRSR_48M BIT10
632 #define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */
661 #define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */
|
| H A D | odm.h | 427 ODM_BB_PATH_DIV = BIT10,
|
| /drivers/staging/rtl8192e/rtl8192e/ |
| H A D | r8192E_hw.h | 232 #define IMR_RXCMDOK BIT10
255 #define TPPoll_StopBE BIT10
385 #define RRSR_48M BIT10
|
| /drivers/scsi/ |
| H A D | tmscsim.h | 182 #define BIT10 0x00000400 macro
217 #define SRB_STATUS BIT10
|
| H A D | dc395x.h | 65 #define BIT10 0x00000400 macro
|
| /drivers/staging/rtl8192e/ |
| H A D | rtl819x_Qos.h | 34 #define BIT10 0x00000400 macro
|
| /drivers/staging/rtl8192u/ieee80211/ |
| H A D | rtl819x_Qos.h | 14 #define BIT10 0x00000400 macro
|
| /drivers/staging/rtl8192u/ |
| H A D | r8192U_hw.h | 317 #define RRSR_48M BIT10
|
| H A D | r8192U.h | 58 #define BIT10 0x00000400 macro
106 #define COMP_TURBO BIT10 /* Turbo Mode */
|
| /drivers/tty/ |
| H A D | synclink.c | 563 #define MISCSTATUS_RI BIT10
585 #define SICR_RI_INACTIVE BIT10
586 #define SICR_RI (BIT11|BIT10)
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
4772 RegValue |= ( BIT12 | BIT10 | BIT9 );
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4971 RegValue |= BIT10;
5172 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5174 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; brea
[all...] |
| H A D | synclink_gt.c | 416 #define IRQ_RXDATA BIT10
2142 if (count == info->rbuf_fill_level || (reg & BIT10)) {
4316 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4318 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4320 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4322 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4389 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4391 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4393 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4395 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; brea
[all...] |
| /drivers/net/wireless/rtlwifi/rtl8192de/ |
| H A D | reg.h | 394 #define RRSR_48M BIT10
|
| /drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 295 #define IRQ_CTS BIT10 // CTS status change
|
| /drivers/scsi/lpfc/ |
| H A D | lpfc_hw4.h | 684 #define LPFC_SLI4_INTR10 BIT10
|