Searched refs:BIT15 (Results 1 - 23 of 23) sorted by relevance

/drivers/net/wireless/rtlwifi/btcoexist/
H A Dhalbt_precomp.h63 #define BIT15 0x00008000 macro
/drivers/staging/emxx_udc/
H A Demxx_udc.h102 #define BIT15 0x00008000 macro
155 #define SOF_STATUS BIT15
184 #define EP7_INT BIT15
211 #define EP7_EN BIT15
252 #define EP0_OUT_NAK_INT BIT15
269 #define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)
273 #define EP0_OUT_NAK_EN BIT15
/drivers/staging/vt6655/
H A D80211hdr.h52 #define BIT15 0x00008000 macro
168 #define WLAN_GET_FC_ORDER(n) ((((unsigned short)(n) << 8) & (BIT15)) >> 15)
201 #define WLAN_GET_FC_ORDER(n) ((((unsigned short)(n)) & (BIT15)) >> 15)
H A Dpower.c77 unsigned short wAID = pMgmt->wCurrAID | BIT14 | BIT15;
244 pTxPacket->p80211Header->sA2.wDurationID = pMgmt->wCurrAID | BIT14 | BIT15;
H A Dwmgr.c962 pMgmt->wCurrAID & ~(BIT14 | BIT15));
2002 wAIDNumber = pMgmt->wCurrAID & ~(BIT14|BIT15);
3821 *sFrame.pwAid = cpu_to_le16((unsigned short)(wAssocAID | BIT14 | BIT15));
3892 *sFrame.pwAid = cpu_to_le16((unsigned short)(wAssocAID | BIT14 | BIT15));
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h194 #define CAM_VALID BIT15
227 #define IMR_TXFOVW BIT15
260 #define TPPoll_StopHCCA BIT15
390 #define RRSR_MCS3 BIT15
H A Drtl_cam.c135 usConfig |= BIT15 | (KeyType<<2);
137 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
/drivers/staging/rtl8188eu/hal/
H A Dodm_RTL8188E.c149 phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2);
349 BIT15, 0);
362 BIT15, 1);
/drivers/staging/rtl8188eu/include/
H A Drtl8188e_spec.h41 #define BIT15 0x00008000 macro
566 #define RRSR_MCS3 BIT15
582 #define CAM_VALID BIT15
628 #define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
657 #define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */
H A Dosdep_service.h122 #define BIT15 0x00008000 macro
/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h39 #define BIT15 0x00008000 macro
/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_Qos.h19 #define BIT15 0x00008000 macro
/drivers/staging/rtl8192u/
H A Dr8192U_hw.h322 #define RRSR_MCS3 BIT15
H A Dr8192U.h63 #define BIT15 0x00008000 macro
111 #define COMP_PHY BIT15
H A Dr8192U_core.c4879 usConfig |= BIT15 | (KeyType<<2);
4881 usConfig |= BIT15 | (KeyType<<2) | KeyIndex;
/drivers/tty/
H A Dsynclink.c558 #define MISCSTATUS_RXC_LATCHED BIT15
578 #define SICR_RXC_ACTIVE BIT15
580 #define SICR_RXC (BIT15|BIT14)
635 #define DICR_MASTER BIT15
1842 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
4719 RegValue |= BIT15;
4721 RegValue |= BIT15 | BIT14;
4763 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4764 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4765 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT1
[all...]
H A Dsynclink_gt.c219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
2145 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
4253 val = BIT15 + BIT14 + BIT0;
4305 val |= BIT15 + BIT13;
4308 case MGSL_MODE_BISYNC: val |= BIT15; break;
4380 val |= BIT15 + BIT13;
4383 case MGSL_MODE_BISYNC: val |= BIT15; break;
4489 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
/drivers/net/ethernet/cirrus/
H A Dcs89x0.h464 #define BIT15 0x8000 macro
/drivers/scsi/
H A Ddc395x.h60 #define BIT15 0x00008000 macro
H A Dtmscsim.h177 #define BIT15 0x00008000 macro
/drivers/net/wireless/rtlwifi/rtl8192de/
H A Dreg.h399 #define RRSR_MCS3 BIT15
/drivers/char/pcmcia/
H A Dsynclink_cs.c290 #define IRQ_BREAK_ON BIT15 // rx break detected
/drivers/scsi/lpfc/
H A Dlpfc_hw4.h689 #define LPFC_SLI4_INTR15 BIT15

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