/drivers/staging/rtl8188eu/include/ |
H A D | rtw_sreset.h | 36 #define WIFI_MAC_TXDMA_ERROR BIT3
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H A D | pwrseq.h | 80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \ 122 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \ 125 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \ 159 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \ 173 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \ 206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
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H A D | odm_debug.h | 63 #define ODM_COMP_FA_CNT BIT3
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H A D | rtl8188e_spec.h | 29 #define BIT3 0x00000008 macro 543 #define CMD_IOCONFIG BIT3 554 #define RRSR_11M BIT3 613 #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 639 #define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ 702 #define StopBK BIT3 729 #define RCR_AB BIT3 /* Accept broadcast packet */ 1203 #define SDIO_HIMR_RXERR_MSK BIT3 1229 #define SDIO_HISR_RXERR BIT3 1300 #define WL_HWROF_EN BIT3 [all...] |
H A D | Hal8188EPhyCfg.h | 94 WIRELESS_MODE_N_24G = BIT3,
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H A D | odm.h | 420 ODM_BB_FA_CNT = BIT3, 466 ODM_RF_TX_D = BIT3, 504 ODM_POWERSAVE = BIT3, 518 ODM_WM_N24G = BIT3, 789 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
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/drivers/staging/vt6655/ |
H A D | hostap.h | 37 #define WLAN_RATE_11M BIT3
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H A D | 80211hdr.h | 40 #define BIT3 0x00000008 macro 159 #define WLAN_GET_FC_FTYPE(n) ((((unsigned short)(n) >> 8) & (BIT2 | BIT3)) >> 2) 171 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3)) 172 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4) 178 #define WLAN_GET_CAP_INFO_CFPOLLREQ(n) ((((n) >> 8) & BIT3) >> 3) 192 #define WLAN_GET_FC_FTYPE(n) ((((unsigned short)(n)) & (BIT2 | BIT3)) >> 2) 204 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3)) 205 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4) 211 #define WLAN_GET_CAP_INFO_CFPOLLREQ(n) (((n) & BIT3) >> 3)
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/drivers/staging/rtl8188eu/hal/ |
H A D | rtl8188eu_led.c | 58 usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); 63 usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6));
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H A D | odm_RTL8188E.c | 64 BIT5|BIT4|BIT3, 0); 169 phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0); 208 BIT5|BIT4|BIT3, default_ant); 217 BIT5|BIT4|BIT3, default_ant);
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/drivers/scsi/ |
H A D | tmscsim.h | 189 #define BIT3 0x00000008 macro 198 #define UNIT_RETRY BIT3 210 #define SRB_MSGIN BIT3 227 #define UNDER_RUN BIT3 282 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */ 337 #define SEND_START_ BIT3 344 #define ACTIVE_NEGATION BIT3 394 #define GROUP_CODE_VALID BIT3 403 #define SUCCESSFUL_OP BIT3 409 #define SYNC_OFFSET_FLAG BIT3 [all...] |
H A D | dc395x.h | 72 #define BIT3 0x00000008 macro 81 #define UNIT_RETRY BIT3 131 #define UNDER_RUN BIT3 176 #define WIDE_NEGO_DONE BIT3 632 #define ACTIVE_NEGATION BIT3
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/drivers/net/wireless/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 51 #define BIT3 0x00000008 macro
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H A D | halbtc8723b2ant.h | 37 #define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
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H A D | halbtc8821a2ant.h | 34 #define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
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H A D | halbtc8192e2ant.h | 34 #define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
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H A D | halbtc8723b1ant.h | 34 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
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H A D | halbtc8821a1ant.h | 36 #define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
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/drivers/net/wireless/rtlwifi/rtl8821ae/ |
H A D | pwrseq.h | 57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ 132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 198 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ 224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ 426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \ 497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT [all...] |
/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ 160 #define RCR_AB BIT3 218 #define SCR_RxDecEnable BIT3 239 #define IMR_BEDOK BIT3 248 #define TPPoll_VOQ BIT3 288 #define AcmHw_VoqEn BIT3 378 #define RRSR_11M BIT3
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/drivers/staging/rtl8192u/ |
H A D | r8192U_hw.h | 157 #define RCR_AB BIT3 // Accept broadcast packet 186 #define SCR_RxDecEnable BIT3 //Enable Rx Decryption 232 #define AcmHw_VoqEn BIT3 310 #define RRSR_11M BIT3
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/drivers/staging/rtl8192e/ |
H A D | rtl819x_Qos.h | 27 #define BIT3 0x00000008 macro 245 #define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) 246 #define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)
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/drivers/staging/rtl8192u/ieee80211/ |
H A D | rtl819x_Qos.h | 7 #define BIT3 0x00000008 macro 387 #define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) 388 #define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)
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/drivers/video/fbdev/via/ |
H A D | dvi.c | 359 BIT0 + BIT1 + BIT2 + BIT3); 384 BIT0 + BIT1 + BIT2 + BIT3); 391 BIT0 + BIT1 + BIT2 + BIT3); 470 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
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H A D | lcd.c | 434 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3); 446 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3); 534 BIT0 + BIT1 + BIT2 + BIT3); 631 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3); 679 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); 773 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); 774 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
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