| /drivers/staging/rtl8188eu/include/ |
| H A D | rtw_sreset.h | 38 #define WIFI_RX_HANG BIT5
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| H A D | rtl8188e_spec.h | 31 #define BIT5 0x00000020 macro
484 #define CmdEEPROM_En BIT5
491 #define GPIOSEL_ENBT BIT5
505 #define HSIMR_SPS_OCP_INT_EN BIT5
512 #define HSISR_SPS_OCP_INT BIT5
545 #define CMD_READ_EFUSE_MAP_ERR BIT5
556 #define RRSR_9M BIT5
584 #define CAM_USEDK BIT5
637 #define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */
700 #define StopHigh BIT5
[all...] |
| H A D | odm_debug.h | 65 #define ODM_COMP_CCK_PD BIT5
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| H A D | Hal8188EPhyCfg.h | 93 WIRELESS_MODE_AUTO = BIT5,
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| H A D | pwrseq.h | 264 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \
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| H A D | odm.h | 422 ODM_BB_CCK_PD = BIT5,
461 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
468 ODM_RF_RX_B = BIT5,
506 ODM_CLIENT_MODE = BIT5,
520 ODM_WM_AUTO = BIT5,
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| H A D | osdep_service.h | 112 #define BIT5 0x00000020 macro
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| /drivers/staging/vt6655/ |
| H A D | hostap.h | 39 #define WLAN_RATE_9M BIT5
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| H A D | 80211hdr.h | 42 #define BIT5 0x00000020 macro
160 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
180 #define WLAN_GET_CAP_INFO_SHORTPREAMBLE(n) ((((n) >> 8) & BIT5) >> 5)
193 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
213 #define WLAN_GET_CAP_INFO_SHORTPREAMBLE(n) (((n) & BIT5) >> 5)
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| H A D | bssdb.h | 62 #define WLAN_STA_AUTHORIZED BIT5
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| /drivers/staging/rtl8188eu/hal/ |
| H A D | rtl8188eu_led.c | 39 usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
63 usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6));
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| H A D | odm_RTL8188E.c | 64 BIT5|BIT4|BIT3, 0);
169 phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0);
208 BIT5|BIT4|BIT3, default_ant);
217 BIT5|BIT4|BIT3, default_ant);
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| /drivers/scsi/ |
| H A D | tmscsim.h | 187 #define BIT5 0x00000020 macro
212 #define SRB_COMMAND BIT5
229 #define SRB_ERROR BIT5
242 #define RESIDUAL_VALID BIT5
284 #define EN_ATN_STOP BIT5
346 #define LUN_CHECK BIT5
392 #define PARITY_ERR BIT5
401 #define DISCONNECTED BIT5
435 #define EN_GRP2_CMD BIT5
444 #define REDUCED_POWER BIT5
[all...] |
| H A D | dc395x.h | 70 #define BIT5 0x00000020 macro
133 #define SRB_ERROR BIT5
138 #define RESIDUAL_VALID BIT5
178 #define EN_TAG_QUEUEING BIT5
634 #define LUN_CHECK BIT5
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| /drivers/net/wireless/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 53 #define BIT5 0x00000020 macro
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| H A D | halbtc8723b2ant.h | 35 #define BT_INFO_8723B_2ANT_B_HID BIT5
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| H A D | halbtc8821a2ant.h | 32 #define BT_INFO_8821A_2ANT_B_HID BIT5
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| H A D | halbtc8192e2ant.h | 32 #define BT_INFO_8192E_2ANT_B_HID BIT5
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| H A D | halbtc8723b1ant.h | 32 #define BT_INFO_8723B_1ANT_B_HID BIT5
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| H A D | halbtc8821a1ant.h | 34 #define BT_INFO_8821A_1ANT_B_HID BIT5
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| /drivers/staging/rtl8192e/rtl8192e/ |
| H A D | r8192E_hw.h | 114 #define EPROM_CMD_RESERVED_MASK BIT5
144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
159 #define RCR_ACRC32 BIT5
196 #define CAM_USEDK BIT5
220 #define SCR_NoSKMC BIT5
237 #define IMR_HCCADOK BIT5
250 #define TPPoll_CQ BIT5
290 #define AcmHw_ViqStatus BIT5
380 #define RRSR_9M BIT5
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| /drivers/staging/rtl8192u/ |
| H A D | r8192U_hw.h | 156 #define RCR_ACRC32 BIT5 // Accept CRC32 error packet
188 #define SCR_NoSKMC BIT5 //No Key Search for Multicast
234 #define AcmHw_ViqStatus BIT5
312 #define RRSR_9M BIT5
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| /drivers/net/wireless/rtlwifi/rtl8821ae/ |
| H A D | pwrseq.h | 284 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
405 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
641 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
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| /drivers/video/fbdev/via/ |
| H A D | dvi.c | 76 BIT5 + BIT6 + BIT7);
80 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
422 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
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| H A D | hw.c | 1711 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
1717 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2080 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
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