| /drivers/staging/vt6655/ |
| H A D | hostap.h | 42 #define WLAN_RATE_24M BIT8
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| H A D | 80211hdr.h | 45 #define BIT8 0x00000100 macro
161 #define WLAN_GET_FC_TODS(n) ((((unsigned short)(n) << 8) & (BIT8)) >> 8)
183 #define WLAN_GET_CAP_INFO_SPECTRUMMNG(n) ((((n)) & BIT8) >> 10)
194 #define WLAN_GET_FC_TODS(n) ((((unsigned short)(n)) & (BIT8)) >> 8)
216 #define WLAN_GET_CAP_INFO_SPECTRUMMNG(n) (((n) & BIT8) >> 10)
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| H A D | device_main.c | 2186 (Key_info & BIT8) && (Key_info & BIT9)) { //send 2/2 key
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| /drivers/net/wireless/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 56 #define BIT8 0x00000100 macro
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| H A D | halbtcoutsrc.h | 109 #define ALGO_TRACE_SW_DETAIL BIT8
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| /drivers/staging/rtl8188eu/hal/ |
| H A D | odm_RTL8188E.c | 41 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);
73 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);
90 BIT10|BIT9|BIT8, 1);
129 phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0);
138 phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1);
146 phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0);
170 phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1);
210 BIT8|BIT7|BIT6, optional_ant);
219 BIT8|BIT7|BIT6, optional_ant);
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| H A D | phy.c | 102 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT8);
104 rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT8);
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| /drivers/staging/rtl8188eu/include/ |
| H A D | odm_debug.h | 68 #define ODM_COMP_PWR_TRA BIT8
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| H A D | rtl8188e_spec.h | 34 #define BIT8 0x00000100 macro
559 #define RRSR_24M BIT8
634 #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
663 #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */
722 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
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| H A D | osdep_service.h | 115 #define BIT8 0x00000100 macro
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| H A D | odm.h | 425 ODM_BB_PWR_TRA = BIT8,
509 ODM_WIFI_DISPLAY = BIT8,
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| /drivers/staging/rtl8192e/rtl8192e/ |
| H A D | r8192E_hw.h | 234 #define IMR_HIGHDOK BIT8
253 #define TPPoll_HCCAQ BIT8
383 #define RRSR_24M BIT8
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| /drivers/scsi/ |
| H A D | tmscsim.h | 184 #define BIT8 0x00000100 macro
215 #define SRB_DATA_XFER BIT8
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| H A D | dc395x.h | 67 #define BIT8 0x00000100 macro
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| /drivers/tty/ |
| H A D | synclink.c | 503 #define RXSTATUS_SHORT_FRAME BIT8
504 #define RXSTATUS_CODE_VIOLATION BIT8
565 #define MISCSTATUS_DSR BIT8
588 #define SICR_DSR_INACTIVE BIT8
589 #define SICR_DSR (BIT9|BIT8)
1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
4548 /* Note: must preserve state of BIT8 in DCAR */
4577 /* Note: must preserve state of BIT8 in DCAR */
4845 RegValue |= BIT9 | BIT8;
4847 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
[all...] |
| H A D | synclink_gt.c | 419 #define IRQ_RXOVER BIT8
2383 if (gsr & (BIT8 << i))
4166 val |= BIT8;
4206 val |= BIT8;
4255 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4328 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4401 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
5044 if (!(*(src+1) & (BIT9 + BIT8))) {
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| /drivers/staging/rtl8192e/ |
| H A D | rtl819x_Qos.h | 32 #define BIT8 0x00000100 macro
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| /drivers/staging/rtl8192u/ieee80211/ |
| H A D | rtl819x_Qos.h | 12 #define BIT8 0x00000100 macro
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| /drivers/staging/rtl8192u/ |
| H A D | r8192U_hw.h | 315 #define RRSR_24M BIT8
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| H A D | r8192U.h | 56 #define BIT8 0x00000100 macro
104 #define COMP_SWBW BIT8 /* Bandwidth switch. */
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| /drivers/net/wireless/rtlwifi/rtl8192de/ |
| H A D | reg.h | 392 #define RRSR_24M BIT8
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| /drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 297 #define IRQ_TXFIFO BIT8 // transmit pool ready
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| /drivers/scsi/lpfc/ |
| H A D | lpfc_hw4.h | 682 #define LPFC_SLI4_INTR8 BIT8
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