Searched refs:PIPECONF (Results 1 - 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/
H A Dintel_dsi_pll.c274 if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
H A Dintel_display.c989 int reg = PIPECONF(cpu_transcoder);
1270 reg = PIPECONF(cpu_transcoder);
1922 pipeconf_val = I915_READ(PIPECONF(pipe));
1966 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2073 reg = PIPECONF(cpu_transcoder);
2111 reg = PIPECONF(cpu_transcoder);
3313 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3383 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3409 /* BPC in FDI rx is consistent with that in PIPECONF */
3411 temp |= (I915_READ(PIPECONF(pip
[all...]
H A Dintel_crt.c558 pipeconf_reg = PIPECONF(pipe);
H A Di915_irq.c733 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
754 * | may be shifted forward 1-3 extra lines via PIPECONF
782 * (depending on PIPECONF settings) after the start of vblank
826 if ((I915_READ(PIPECONF(cpu_transcoder)) &
H A Di915_reg.h3818 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) macro
H A Dintel_dp.c4876 reg = PIPECONF(intel_crtc->config.cpu_transcoder);

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