Searched refs:PIPESTAT (Results 1 - 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/
H A Di915_irq.c318 u32 reg = PIPESTAT(crtc->pipe);
342 u32 reg = PIPESTAT(pipe);
588 u32 reg = PIPESTAT(pipe);
614 u32 reg = PIPESTAT(pipe);
2028 * PIPESTAT bits get signalled even when the interrupt is
2055 reg = PIPESTAT(pipe);
2790 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
3421 I915_WRITE(PIPESTAT(pipe), 0xffff);
3491 I915_WRITE(PIPESTAT(pipe), 0xffff);
3642 I915_WRITE(PIPESTAT(PIPE_
[all...]
H A Di915_debugfs.c682 I915_READ(PIPESTAT(pipe)));
769 I915_READ(PIPESTAT(pipe)));
805 I915_READ(PIPESTAT(pipe)));
H A Di915_reg.h3822 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) macro
H A Dintel_display.c915 int pipestat_reg = PIPESTAT(pipe);
13699 error->pipe[i].stat = I915_READ(PIPESTAT(i));

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