Searched refs:RCR (Results 1 - 22 of 22) sorted by relevance

/drivers/staging/rtl8712/
H A Drtl8712_cmdctrl_regdef.h27 #define RCR (RTL8712_CMDCTRL_ + 0x0008) macro
H A Dhal_init.c335 netdev_info(padapter->pnetdev, "1 RCR=0x%x\n",
336 r8712_read32(padapter, RCR));
337 val32 = r8712_read32(padapter, RCR);
338 r8712_write32(padapter, RCR, (val32 | BIT(26))); /* Enable RX TCP
340 netdev_info(padapter->pnetdev, "2 RCR=0x%x\n",
341 r8712_read32(padapter, RCR));
342 val32 = r8712_read32(padapter, RCR);
343 r8712_write32(padapter, RCR, (val32|BIT(25))); /* Append PHY status */
H A Drtl871x_mp_ioctl.c294 r8712_write8(Adapter, RCR, 0); /* RCR : disable all pkt, 0x10250048 */
295 /* RCR disable Check BSSID, 0x1025004a */
296 r8712_write8(Adapter, RCR+2, 0x57);
1353 rcr_val32 = r8712_read32(Adapter, RCR);/*RCR = 0x10250048*/
1377 r8712_write32(Adapter, RCR, rcr_val32);
/drivers/net/ethernet/smsc/
H A Dsmc9194.h80 #define RCR 4 macro
87 /* the normal settings for the RCR register : */
207 #define SMC_DELAY() { inw( ioaddr + RCR );\
208 inw( ioaddr + RCR );\
209 inw( ioaddr + RCR ); }
H A Dsmc9194.c324 outw( RCR_SOFTRESET, ioaddr + RCR );
331 outw( RCR_CLEAR, ioaddr + RCR );
362 /* see the header file for options in TCR/RCR NORMAL*/
364 outw( RCR_NORMAL, ioaddr + RCR );
393 outb( RCR_CLEAR, ioaddr + RCR );
1485 outw( inw(ioaddr + RCR ) | RCR_PROMISC, ioaddr + RCR ); local
1497 outw( inw(ioaddr + RCR ) | RCR_ALMUL, ioaddr + RCR ); local
1506 outw( inw( ioaddr + RCR )
1507 ioaddr + RCR ); local
1514 ioaddr + RCR ); local
[all...]
H A Dsmc91c92_cs.c224 #define RCR 4 macro
233 /* the normal settings for the RCR register : */
1100 mask_bits(0xff00, ioaddr + RCR);
1578 outw(rx_cfg_setting, ioaddr + RCR);
1650 outw(RCR_SOFTRESET, ioaddr + RCR);
1654 outw(RCR_CLEAR, ioaddr + RCR);
/drivers/net/usb/
H A Dsr9700.h57 #define RCR 0x05 macro
H A Drtl8150.c28 #define RCR 0x0130 macro
620 /* RCR bit7=1 attach Rx info at the end; =0 HW CRC (which is broken) */
626 set_registers(dev, RCR, 1, &rcr);
669 async_set_registers(dev, RCR, sizeof(rx_creg), rx_creg);
H A Dsr9700.c285 sr_write_reg_async(dev, RCR, rx_ctl);
/drivers/rtc/
H A Drtc-r9701.c41 #define RCR 0x0f /* RTC Control Register */ macro
/drivers/net/wireless/rtlwifi/rtl8192se/
H A Dfw.c321 /* If right here, we can set TCR/RCR to desired value */
326 tmpu4b = rtl_read_dword(rtlpriv, RCR);
327 rtl_write_dword(rtlpriv, RCR, (tmpu4b | RCR_APPFCS |
331 "Current RCR settings(%#x)\n", tmpu4b);
H A Dhw.c311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
793 /* Set RCR */
794 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1013 /* because last function modify RCR, so we update
1018 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1020 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
H A Dreg.h62 #define RCR 0x0048 macro
/drivers/staging/rtl8192u/
H A Dr8192U_hw.h130 RCR = 0x044, // Receive Configuration Register enumerator in enum:_RTL8192Usb_HW
H A Dr8192U_core.c755 read_nic_dword(dev, RCR, &rxconf);
790 write_nic_dword(dev, RCR, rxconf);
1784 read_nic_dword(dev, RCR, &reg);
1789 write_nic_dword(dev, RCR, reg);
2708 //set RCR
2709 write_nic_dword(dev, RCR, priv->ReceiveConfig);
/drivers/tty/
H A Dsynclink_gt.c398 #define RCR 0x86 /* rx control */ macro
2746 /* force hunt mode (write 1 to RCR[3]) */
2747 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
3984 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3985 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3986 wr_reg16(info, RCR, val); /* clear reset bit */
4009 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4010 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4011 wr_reg16(info, RCR, va
[all...]
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_dev.c146 RegRCR = read_nic_dword(dev, RCR);
154 write_nic_dword(dev, RCR, RegRCR);
783 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1014 reg = read_nic_dword(dev, RCR);
1023 write_nic_dword(dev, RCR, reg);
1038 write_nic_dword(dev, RCR, priv->ReceiveConfig);
H A Dr8192E_hw.h143 RCR = 0x044, enumerator in enum:_RTL8192Pci_HW
/drivers/spi/
H A Dspi-atmel.c133 /* Bitfields in RCR */
749 spi_writel(as, RCR, len);
1136 spi_readl(as, TCR), spi_readl(as, RCR));
1144 spi_writel(as, RCR, 0);
/drivers/net/wan/
H A Dhd64572.h110 #define RCR 0x156 /* Rx DMA Critical Request Reg */ macro
/drivers/net/ethernet/via/
H A Dvia-velocity.h403 * Bits in the RCR register
979 volatile u8 RCR; member in struct:mac_regs
H A Dvia-velocity.c1170 BYTE_REG_BITS_ON(rx_mode, &regs->RCR);

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