/drivers/video/fbdev/omap2/dss/ |
H A D | hdmi5_core.c | 69 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); 75 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); 79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, 81 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, 86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, 88 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, 93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, 95 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, 100 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, 102 REG_FLD_MOD(bas [all...] |
H A D | hdmi4_core.c | 54 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); 59 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); 69 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); 79 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); 110 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); 113 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); 116 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); 119 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); 120 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); 124 REG_FLD_MOD(bas [all...] |
H A D | hdmi_phy.c | 131 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); 132 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); 150 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); 171 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); 178 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
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H A D | dss.c | 63 #define REG_FLD_MOD(idx, val, start, end) \ macro 185 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 189 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 201 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 229 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 243 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 322 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ 355 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ 395 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ 531 REG_FLD_MOD(DSS_CONTRO [all...] |
H A D | hdmi_wp.c | 76 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); 92 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); 106 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); 113 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); 121 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 228 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); 235 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
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H A D | hdmi_pll.c | 113 REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); 134 REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10); 142 REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0); 172 REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, pll_feat->sys_reset, 3, 3);
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H A D | dispc.c | 58 #define REG_FLD_MOD(idx, val, start, end) \ macro 258 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); 582 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); 679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 768 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 779 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 788 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 801 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 892 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 902 REG_FLD_MOD(DISPC_OVL_ATTRIBUTE [all...] |
H A D | dsi.c | 123 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ macro 1249 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1336 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1339 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1349 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1358 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1379 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1575 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); 1616 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ 2032 REG_FLD_MOD(dside [all...] |
H A D | hdmi5.c | 124 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); 347 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); 351 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
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H A D | hdmi.h | 282 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
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H A D | rfbi.c | 69 #define REG_FLD_MOD(idx, val, start, end) \ macro 345 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); 457 REG_FLD_MOD(RFBI_CONFIG(rfbi_module), 729 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
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/drivers/gpu/drm/gma500/ |
H A D | mdfld_dsi_dpi.c | 113 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); 146 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); 150 REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); 154 REG_FLD_MOD(dspcntr_reg, 0, 31, 31); 161 REG_FLD_MOD(pipeconf_reg, 0, 31, 31); 476 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); 565 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0);
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H A D | mdfld_dsi_output.h | 50 #define REG_FLD_MOD(reg, val, start, end) \ macro
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