Searched refs:SM (Results 1 - 24 of 24) sorted by relevance

/drivers/net/wireless/ath/ath9k/
H A Dar9003_rtt.c77 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
80 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
81 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
82 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
86 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
95 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
146 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
147 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
148 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
153 val |= SM(
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H A Dbtcoex.c76 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
77 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
78 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
79 SM(ath_bt_config.bt_mode, AR_BT_MODE) |
80 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
81 SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
82 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
83 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
84 SM(qnum, AR_BT_QCU_THRESH);
87 SM(ath_bt_confi
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H A Dar9002_mac.c227 ctl6 = SM(i->keytype, AR_EncrType);
243 | SM(0, AR_BurstDur);
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
262 | SM(i->type, AR_FrameType)
269 ctl6 |= SM(i->aggr_len, AR_AggrLen);
273 ctl6 |= SM(i->ndelim, AR_PadDelim);
284 | SM(i->txpower, AR_XmitPower0)
308 | SM(i->rtscts_rate, AR_RTSCTSRate);
310 ACCESS_ONCE(ads->ds_ctl9) = SM(i->txpower, AR_XmitPower1);
311 ACCESS_ONCE(ads->ds_ctl10) = SM(
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H A Deeprom_9287.c499 regval = SM(pdGainOverlap_t2,
501 | SM(gainBoundaries[0],
503 | SM(gainBoundaries[1],
505 | SM(gainBoundaries[2],
507 | SM(gainBoundaries[3],
915 SM(pModal->iqCalICh[i],
917 SM(pModal->iqCalQCh[i],
948 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
949 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
950 | SM(pModa
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H A Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
398 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
399 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
400 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
403 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
404 SM(INIT_SLG_RETR
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H A Dar9002_phy.c255 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
284 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
285 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
464 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
465 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
468 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
470 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
606 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL);
607 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);
608 regval |= SM((antdiv_ctrl
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H A Dar9003_mac.c74 | SM(0, AR_BurstDur);
90 ctl17 = SM(i->keytype, AR_EncrType);
104 | SM(i->txpower, AR_XmitPower0)
113 SM(i->keyix, AR_DestIdx) : 0)
114 | SM(i->type, AR_FrameType)
122 ctl17 |= SM(i->aggr_len, AR_AggrLen);
126 ctl17 |= SM(i->ndelim, AR_PadDelim);
136 ctl12 |= SM(val, AR_PAPRDChainMask);
151 | SM(i->rtscts_rate, AR_RTSCTSRate);
155 ACCESS_ONCE(ads->ctl20) = SM(
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H A Dar5008_phy.c309 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
319 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
320 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
878 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
881 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
883 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
886 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
888 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
901 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
903 pll |= SM(
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H A Dar9003_mci.c854 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
855 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
856 SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
857 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
858 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
859 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
860 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
862 regval |= SM(1, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
863 SM(1, AR_BTCOEX_CTRL_RX_CHAIN_MASK);
867 regval |= SM(
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H A Deeprom_4k.c415 SM(pdGainOverlap_t2,
417 | SM(gainBoundaries[0],
419 | SM(gainBoundaries[1],
421 | SM(gainBoundaries[2],
423 | SM(gainBoundaries[3],
766 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
767 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
841 regVal |= SM(ant_div_control1,
843 regVal |= SM(ant_div_control2,
845 regVal |= SM((ant_div_control
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H A Deeprom_def.c500 | SM(pModal-> bswMargin[i],
505 | SM(pModal->bswAtten[i],
522 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
527 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
562 SM(pModal->iqCalICh[i],
564 SM(pModal->iqCalQCh[i],
631 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
632 | SM(pModal->txEndToXpaOff,
634 | SM(pModal->txFrameToXpaOn,
636 | SM(pModa
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H A Dar9003_phy.c525 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
528 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
530 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
532 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
542 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
545 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
547 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
549 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
1372 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1373 radar_0 |= SM(con
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H A Dmac.h21 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
24 (SM((_series)[_index].Rate, AR_XmitRate##_index))
27 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
38 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
H A Dhw.c661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1063 SM(rx_lat, AR_USEC_RX_LAT) |
1064 SM(tx_lat, AR_USEC_TX_LAT),
2242 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2251 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2952 mask |= SM(AR_GENTMR_BIT(timer->index),
2955 mask |= SM(AR_GENTMR_BIT(timer->index),
2987 (SM(AR_GENTMR_BI
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H A Dhw.h107 #define SM(_v, _f) (((_v) << _f##_S) & _f) macro
/drivers/net/wireless/ath/ath6kl/
H A Dhif.c216 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
219 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
580 SM(INT_STATUS_ENABLE_ERROR, 0x01) |
581 SM(INT_STATUS_ENABLE_CPU, 0x01) |
582 SM(INT_STATUS_ENABLE_COUNTER, 0x01);
588 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01);
595 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) |
596 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1);
602 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT,
H A Dtarget.h133 #define SM(f, v) (((v) << f##_S) & f) macro
H A Dinit.c1447 param |= SM(SYSTEM_SLEEP_DISABLE, 1);
1465 param = SM(CPU_CLOCK_STANDARD, 1);
1475 param = SM(LPO_CAL_ENABLE, 1);
/drivers/net/wireless/ath/ath10k/
H A Dhtt_tx.c502 flags0 |= SM(ATH10K_HW_TXRX_NATIVE_WIFI,
507 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
541 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
542 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
H A Dcore.h39 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) macro
H A Dwmi.c665 cmd |= SM(cmd_id, WMI_CMD_HDR_CMD_ID);
4076 info0 = SM(max_mcs, WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX) |
4077 SM(max_nss, WMI_PEER_ASSOC_INFO0_MAX_NSS);
4247 cfg = SM(ATH10K_DBGLOG_LEVEL_VERBOSE,
4251 cfg = SM(ATH10K_DBGLOG_LEVEL_WARN,
H A Dce.c299 desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA);
H A Dhtc.c680 flags |= SM(tx_alloc, ATH10K_HTC_CONN_FLAGS_RECV_ALLOC);
H A Dmac.c715 rts_cts |= SM(WMI_RTSCTS_ENABLED, WMI_RTSCTS_SET);
718 rts_cts |= SM(WMI_RTSCTS_ACROSS_SW_RETRIES,

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