Searched refs:SYS_GPCPLL_CFG_BASE (Results 1 - 1 of 1) sorted by relevance

/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dgk20a.c30 #define SYS_GPCPLL_CFG_BASE 0x00137000 macro
33 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
39 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4)
47 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc)
51 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)
54 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)
61 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100)
64 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)

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