/drivers/staging/rtl8712/ |
H A D | rtl8712_cmdctrl_regdef.h | 26 #define TCR (RTL8712_CMDCTRL_ + 0x0004) macro
|
H A D | hal_init.c | 215 tmp16 = r8712_read16(padapter, TCR); 218 tmp16 = r8712_read16(padapter, TCR); 243 tmp16 = r8712_read16(padapter, TCR); 246 tmp16 = r8712_read16(padapter, TCR); 265 tmp32 = r8712_read32(padapter, TCR); 269 tmp16 = r8712_read16(padapter, TCR); 272 tmp16 = r8712_read16(padapter, TCR); 294 tmp16 = r8712_read16(padapter, TCR); 297 tmp16 = r8712_read16(padapter, TCR); 309 tmp16 = r8712_read16(padapter, TCR); [all...] |
H A D | usb_halinit.c | 275 val8 = r8712_read8(padapter, TCR);
|
/drivers/clocksource/ |
H A D | timer-keystone.c | 28 #define TCR 0x20 macro 83 tcr = keystone_timer_readl(TCR); 99 keystone_timer_writel(off, TCR); 115 keystone_timer_writel(tcr, TCR); 123 tcr = keystone_timer_readl(TCR); 127 keystone_timer_writel(tcr, TCR); 196 keystone_timer_writel(0, TCR);
|
H A D | sh_tmu.c | 77 #define TCR 2 /* channel register */ macro 103 if (reg_nr == TCR) 125 if (reg_nr == TCR) 169 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); 194 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); 221 sh_tmu_read(ch, TCR); 224 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); 244 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); 246 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
|
H A D | sh_mtu2.c | 60 #define TCR 0 /* channel register */ macro 151 [TCR] = 0, 235 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
|
/drivers/watchdog/ |
H A D | davinci_wdt.c | 37 #define TCR (0x20) macro 41 /* TCR bit definitions */ 81 iowrite32(0, davinci_wdt->base + TCR); 95 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); 97 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
|
/drivers/net/wireless/rtlwifi/rtl8192se/ |
H A D | fw.c | 66 cpustatus = rtl_read_byte(rtlpriv, TCR); 239 cpustatus = rtl_read_byte(rtlpriv, TCR); 257 cpustatus = rtl_read_byte(rtlpriv, TCR); 282 cpustatus = rtl_read_byte(rtlpriv, TCR); 303 cpustatus = rtl_read_byte(rtlpriv, TCR); 321 /* If right here, we can set TCR/RCR to desired value */ 323 tmpu4b = rtl_read_dword(rtlpriv, TCR); 324 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
|
H A D | hw.c | 601 rtl_write_byte(rtlpriv, TCR, 0); 741 tmpu1b = rtl_read_byte(rtlpriv, TCR); 750 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", 789 /* Set TCR TX DMA pre 2 FULL enable bit */ 790 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | 1209 temp = rtl_read_dword(rtlpriv, TCR); 1210 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); 1211 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); 1453 rtl_write_byte(rtlpriv, TCR, [all...] |
/drivers/net/ethernet/smsc/ |
H A D | smc9194.h | 64 #define TCR 0 /* transmit control register */ macro 72 /* the normal settings for the TCR register : */
|
H A D | smc91c92_cs.c | 148 #define TCR 0 /* transmit control register */ macro 1101 mask_bits(0xff00, ioaddr + TCR); 1297 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); local 1332 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); local 1655 outw(TCR_CLEAR, ioaddr + TCR); 1684 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR); 1790 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR); local [all...] |
H A D | smc9194.c | 332 outw( TCR_CLEAR, ioaddr + TCR ); 362 /* see the header file for options in TCR/RCR NORMAL*/ 363 outw( TCR_NORMAL, ioaddr + TCR ); 394 outb( TCR_CLEAR, ioaddr + TCR ); 1313 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR ); local
|
/drivers/net/usb/ |
H A D | sr9700.h | 33 #define TCR 0x02 macro
|
H A D | rtl8150.c | 27 #define TCR 0x012f macro 627 set_registers(dev, TCR, 1, &tcr);
|
/drivers/net/ethernet/amd/ |
H A D | ariadne.h | 381 volatile u_char TCR; /* Timer Control Register */ member in struct:MC68230
|
/drivers/tty/ |
H A D | synclink_gt.c | 395 #define TCR 0x82 /* tx control */ macro 1422 value = rd_reg16(info, TCR); 1427 wr_reg16(info, TCR, value); 2302 unsigned short val = rd_reg16(info, TCR); 2303 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 2304 wr_reg16(info, TCR, val); /* clear reset bit */ 2893 /* TCR (tx control) 07 1=RTS driver control */ 2894 val = rd_reg16(info, TCR); 2899 wr_reg16(info, TCR, val); 4051 wr_reg16(info, TCR, [all...] |
/drivers/staging/rtl8192u/ |
H A D | r8192U_hw.h | 123 TCR = 0x040, // Transmit Configuration Register enumerator in enum:_RTL8192Usb_HW
|
/drivers/dma/sh/ |
H A D | shdmac.c | 44 #define TCR 0x08 /* Transfer Count Register */ macro 223 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); 427 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
|
/drivers/spi/ |
H A D | spi-atmel.c | 137 /* Bitfields in TCR */ 750 spi_writel(as, TCR, len); 1136 spi_readl(as, TCR), spi_readl(as, RCR)); 1145 spi_writel(as, TCR, 0);
|
/drivers/net/ethernet/cadence/ |
H A D | at91_ether.c | 174 macb_writel(lp, TCR, skb->len);
|
/drivers/net/wan/ |
H A D | hd64572.h | 108 #define TCR 0x152 /* Tx DMA Critical Request Reg */ macro
|
H A D | hd64572.c | 459 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
|
/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 142 TCR = 0x040, enumerator in enum:_RTL8192Pci_HW
|
/drivers/net/ethernet/via/ |
H A D | via-velocity.c | 950 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR); 956 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR); 1852 BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR); 1854 BYTE_REG_BITS_OFF(TCR_TB2BDIS, ®s->TCR); 2582 td_ptr->tdesc1.TCR = TCR0_TIC; 2616 td_ptr->tdesc1.TCR |= TCR0_VETAG; 2625 td_ptr->tdesc1.TCR |= TCR0_TCPCK; 2627 td_ptr->tdesc1.TCR |= (TCR0_UDPCK); 2628 td_ptr->tdesc1.TCR |= TCR0_IPCK;
|
H A D | via-velocity.h | 209 u8 TCR; member in struct:tdesc1 416 * Bits in the TCR register 980 volatile u8 TCR; member in struct:mac_regs
|