Searched refs:TCR (Results 1 - 25 of 26) sorted by relevance

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/drivers/staging/rtl8712/
H A Drtl8712_cmdctrl_regdef.h26 #define TCR (RTL8712_CMDCTRL_ + 0x0004) macro
H A Dhal_init.c215 tmp16 = r8712_read16(padapter, TCR);
218 tmp16 = r8712_read16(padapter, TCR);
243 tmp16 = r8712_read16(padapter, TCR);
246 tmp16 = r8712_read16(padapter, TCR);
265 tmp32 = r8712_read32(padapter, TCR);
269 tmp16 = r8712_read16(padapter, TCR);
272 tmp16 = r8712_read16(padapter, TCR);
294 tmp16 = r8712_read16(padapter, TCR);
297 tmp16 = r8712_read16(padapter, TCR);
309 tmp16 = r8712_read16(padapter, TCR);
[all...]
H A Dusb_halinit.c275 val8 = r8712_read8(padapter, TCR);
/drivers/clocksource/
H A Dtimer-keystone.c28 #define TCR 0x20 macro
83 tcr = keystone_timer_readl(TCR);
99 keystone_timer_writel(off, TCR);
115 keystone_timer_writel(tcr, TCR);
123 tcr = keystone_timer_readl(TCR);
127 keystone_timer_writel(tcr, TCR);
196 keystone_timer_writel(0, TCR);
H A Dsh_tmu.c77 #define TCR 2 /* channel register */ macro
103 if (reg_nr == TCR)
125 if (reg_nr == TCR)
169 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
194 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
221 sh_tmu_read(ch, TCR);
224 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
244 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
246 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
H A Dsh_mtu2.c60 #define TCR 0 /* channel register */ macro
151 [TCR] = 0,
235 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
/drivers/watchdog/
H A Ddavinci_wdt.c37 #define TCR (0x20) macro
41 /* TCR bit definitions */
81 iowrite32(0, davinci_wdt->base + TCR);
95 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
97 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
/drivers/net/wireless/rtlwifi/rtl8192se/
H A Dfw.c66 cpustatus = rtl_read_byte(rtlpriv, TCR);
239 cpustatus = rtl_read_byte(rtlpriv, TCR);
257 cpustatus = rtl_read_byte(rtlpriv, TCR);
282 cpustatus = rtl_read_byte(rtlpriv, TCR);
303 cpustatus = rtl_read_byte(rtlpriv, TCR);
321 /* If right here, we can set TCR/RCR to desired value */
323 tmpu4b = rtl_read_dword(rtlpriv, TCR);
324 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
H A Dhw.c601 rtl_write_byte(rtlpriv, TCR, 0);
741 tmpu1b = rtl_read_byte(rtlpriv, TCR);
750 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
789 /* Set TCR TX DMA pre 2 FULL enable bit */
790 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
1209 temp = rtl_read_dword(rtlpriv, TCR);
1210 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1211 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1453 rtl_write_byte(rtlpriv, TCR,
[all...]
/drivers/net/ethernet/smsc/
H A Dsmc9194.h64 #define TCR 0 /* transmit control register */ macro
72 /* the normal settings for the TCR register : */
H A Dsmc91c92_cs.c148 #define TCR 0 /* transmit control register */ macro
1101 mask_bits(0xff00, ioaddr + TCR);
1297 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); local
1332 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); local
1655 outw(TCR_CLEAR, ioaddr + TCR);
1684 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR);
1790 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR); local
[all...]
H A Dsmc9194.c332 outw( TCR_CLEAR, ioaddr + TCR );
362 /* see the header file for options in TCR/RCR NORMAL*/
363 outw( TCR_NORMAL, ioaddr + TCR );
394 outb( TCR_CLEAR, ioaddr + TCR );
1313 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR ); local
/drivers/net/usb/
H A Dsr9700.h33 #define TCR 0x02 macro
H A Drtl8150.c27 #define TCR 0x012f macro
627 set_registers(dev, TCR, 1, &tcr);
/drivers/net/ethernet/amd/
H A Dariadne.h381 volatile u_char TCR; /* Timer Control Register */ member in struct:MC68230
/drivers/tty/
H A Dsynclink_gt.c395 #define TCR 0x82 /* tx control */ macro
1422 value = rd_reg16(info, TCR);
1427 wr_reg16(info, TCR, value);
2302 unsigned short val = rd_reg16(info, TCR);
2303 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2304 wr_reg16(info, TCR, val); /* clear reset bit */
2893 /* TCR (tx control) 07 1=RTS driver control */
2894 val = rd_reg16(info, TCR);
2899 wr_reg16(info, TCR, val);
4051 wr_reg16(info, TCR,
[all...]
/drivers/staging/rtl8192u/
H A Dr8192U_hw.h123 TCR = 0x040, // Transmit Configuration Register enumerator in enum:_RTL8192Usb_HW
/drivers/dma/sh/
H A Dshdmac.c44 #define TCR 0x08 /* Transfer Count Register */ macro
223 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
427 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
/drivers/spi/
H A Dspi-atmel.c137 /* Bitfields in TCR */
750 spi_writel(as, TCR, len);
1136 spi_readl(as, TCR), spi_readl(as, RCR));
1145 spi_writel(as, TCR, 0);
/drivers/net/ethernet/cadence/
H A Dat91_ether.c174 macb_writel(lp, TCR, skb->len);
/drivers/net/wan/
H A Dhd64572.h108 #define TCR 0x152 /* Tx DMA Critical Request Reg */ macro
H A Dhd64572.c459 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h142 TCR = 0x040, enumerator in enum:_RTL8192Pci_HW
/drivers/net/ethernet/via/
H A Dvia-velocity.c950 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
956 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
1852 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
1854 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
2582 td_ptr->tdesc1.TCR = TCR0_TIC;
2616 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2625 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2627 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2628 td_ptr->tdesc1.TCR |= TCR0_IPCK;
H A Dvia-velocity.h209 u8 TCR; member in struct:tdesc1
416 * Bits in the TCR register
980 volatile u8 TCR; member in struct:mac_regs

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