Searched refs:VLV_DISPLAY_BASE (Results 1 - 4 of 4) sorted by relevance
/drivers/gpu/drm/i915/ |
H A D | i915_reg.h | 490 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 507 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 508 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 726 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) 1253 #define VLV_DISPLAY_BASE 0x180000 macro 1254 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 1256 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) 1257 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) 1263 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) 1266 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE [all...] |
H A D | i915_drv.c | 261 .display_mmio_offset = VLV_DISPLAY_BASE, 272 .display_mmio_offset = VLV_DISPLAY_BASE, 354 .display_mmio_offset = VLV_DISPLAY_BASE,
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H A D | intel_i2c.c | 527 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
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H A D | intel_display.c | 12368 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) 12369 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, 12371 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || 12373 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); 12375 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) 12376 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, 12378 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || 12380 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); 12383 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) 12384 intel_hdmi_init(dev, VLV_DISPLAY_BASE [all...] |
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