| /drivers/gpu/drm/gma500/ |
| H A D | gem.h | 20 u64 size, u32 *handlep, int stolen, u32 align);
|
| /drivers/gpu/drm/nouveau/core/subdev/fb/ |
| H A D | ramgk20a.c | 53 gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, argument
62 nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size,
63 align, ncmin);
69 if (align == 0)
70 align = PAGE_SIZE;
71 align >>= PAGE_SHIFT;
74 order = fls(align);
75 if ((align & (align - 1)) == 0)
77 align
[all...] |
| /drivers/gpu/drm/nouveau/core/engine/graph/fuc/ |
| H A D | gpcgm107.fuc5 | 41 .align 256
|
| H A D | gpcnv108.fuc5 | 41 .align 256
|
| H A D | gpcnvc0.fuc | 41 .align 256
|
| H A D | gpcnvd7.fuc | 41 .align 256
|
| H A D | gpcnve0.fuc | 41 .align 256
|
| H A D | gpcnvf0.fuc | 41 .align 256
|
| H A D | hubgm107.fuc5 | 39 .align 256
|
| H A D | hubnv108.fuc5 | 39 .align 256
|
| H A D | hubnvc0.fuc | 39 .align 256
|
| H A D | hubnvd7.fuc | 39 .align 256
|
| H A D | hubnve0.fuc | 39 .align 256
|
| H A D | hubnvf0.fuc | 39 .align 256
|
| /drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/ |
| H A D | nv108.fuc | 57 .align 256
70 .align 256
|
| H A D | nva3.fuc | 57 .align 256
70 .align 256
|
| H A D | nvc0.fuc | 57 .align 256
70 .align 256
|
| H A D | nvd0.fuc | 57 .align 256
70 .align 256
|
| /drivers/staging/fwserial/ |
| H A D | dma_fifo.h | 58 unsigned align; /* must be power of 2 */ member in struct:dma_fifo
85 int dma_fifo_alloc(struct dma_fifo *fifo, int size, unsigned align,
121 tx_limit = round_down(tx_limit, fifo->align);
122 fifo->tx_limit = max_t(int, tx_limit, fifo->align);
|
| H A D | dma_fifo.c | 57 * @align: dma alignment to maintain (should be at least cpu cache alignment),
60 * multiple of alignment, but at least align size)
67 int dma_fifo_alloc(struct dma_fifo *fifo, int size, unsigned align, argument
72 if (!is_power_of_2(align) || size < 0)
75 size = round_up(size, align);
76 capacity = size + align * open_limit + align * DMA_FIFO_GUARD;
86 fifo->align = align;
87 fifo->tx_limit = max_t(int, round_down(tx_limit, align), alig
[all...] |
| /drivers/gpu/drm/radeon/ |
| H A D | radeon_sa.c | 52 unsigned size, u32 align, u32 domain, u32 flags)
60 sa_manager->align = align;
67 r = radeon_bo_create(rdev, size, align, true,
192 unsigned size, unsigned align)
198 wasted = (align - (soffset % align)) % align;
219 * @align: alignment we need to match
225 unsigned size, unsigned align)
50 radeon_sa_bo_manager_init(struct radeon_device *rdev, struct radeon_sa_manager *sa_manager, unsigned size, u32 align, u32 domain, u32 flags) argument
190 radeon_sa_bo_try_alloc(struct radeon_sa_manager *sa_manager, struct radeon_sa_bo *sa_bo, unsigned size, unsigned align) argument
224 radeon_sa_event(struct radeon_sa_manager *sa_manager, unsigned size, unsigned align) argument
312 radeon_sa_bo_new(struct radeon_device *rdev, struct radeon_sa_manager *sa_manager, struct radeon_sa_bo **sa_bo, unsigned size, unsigned align) argument
[all...] |
| /drivers/gpu/drm/nouveau/core/include/core/ |
| H A D | mm.h | 35 u32 size_min, u32 align, struct nouveau_mm_node **);
37 u32 size_min, u32 align, struct nouveau_mm_node **);
|
| H A D | ramht.h | 15 u32 size, u32 align, struct nouveau_ramht **);
|
| /drivers/pcmcia/ |
| H A D | rsrc_iodyn.c | 31 resource_size_t size, resource_size_t align)
60 unsigned long align)
68 data.mask = align - 1;
89 unsigned int align, struct resource **parent)
104 if ((s->io[i].res->start & (align-1)) == *base)
117 if (align == 0)
118 align = 0x10000;
121 num, align);
29 pcmcia_align(void *align_data, const struct resource *res, resource_size_t size, resource_size_t align) argument
58 __iodyn_find_io_region(struct pcmcia_socket *s, unsigned long base, int num, unsigned long align) argument
87 iodyn_find_io(struct pcmcia_socket *s, unsigned int attr, unsigned int *base, unsigned int num, unsigned int align, struct resource **parent) argument
|
| /drivers/base/ |
| H A D | dma-contiguous.c | 183 * @align: Requested alignment of pages (in PAGE_SIZE order).
191 unsigned int align)
193 if (align > CONFIG_CMA_ALIGNMENT)
194 align = CONFIG_CMA_ALIGNMENT;
196 return cma_alloc(dev_get_cma_area(dev), count, align);
245 phys_addr_t align = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order); local
246 phys_addr_t mask = align - 1;
190 dma_alloc_from_contiguous(struct device *dev, int count, unsigned int align) argument
|