Searched refs:dclk (Results 1 - 25 of 26) sorted by relevance

12

/drivers/video/fbdev/riva/
H A Dnv_driver.c275 unsigned long dclk = 0; local
285 dclk = 800000;
287 dclk = 1000000;
293 dclk = 1000000;
302 dclk = 800000;
305 dclk = 1000000;
310 return dclk;
/drivers/clk/samsung/
H A DMakefile16 obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk))
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
588 (new_ps->dclk == old_ps->dclk))
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
731 rps->dclk = 0;
735 if ((rps->vclk == 0) || (rps->dclk == 0)) {
737 rps->dclk
[all...]
H A Dtrinity_dpm.h70 u32 dclk; member in struct:trinity_uvd_clock_table_entry
H A Drv770_dpm.c1438 (new_ps->dclk == old_ps->dclk))
1444 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1455 (new_ps->dclk == old_ps->dclk))
1461 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
2151 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2154 rps->dclk = 0;
2158 if ((rps->vclk == 0) || (rps->dclk == 0)) {
2160 rps->dclk
[all...]
H A Dtrinity_dpm.c896 if ((rps->vclk == 0) && (rps->dclk == 0))
909 (rps1->dclk == rps2->dclk) &&
941 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
952 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
1439 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
1625 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1628 rps->dclk = 0;
1854 pi->sys_info.uvd_clock_table_entries[i].dclk
[all...]
H A Dradeon_asic.h408 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
470 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
527 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
528 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
727 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
754 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
H A Dradeon_uvd.c853 * @dclk: wanted DCLK
863 * @optimal_dclk_div: resulting dclk post divider
869 unsigned vclk, unsigned dclk,
884 vco_min = max(max(vco_min, vclk), dclk);
904 /* calc dclk divider with current vco freq */
905 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
911 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
868 radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, unsigned vclk, unsigned dclk, unsigned vco_min, unsigned vco_max, unsigned fb_factor, unsigned fb_mask, unsigned pd_min, unsigned pd_max, unsigned pd_even, unsigned *optimal_fb_div, unsigned *optimal_vclk_div, unsigned *optimal_dclk_div) argument
H A Drv6xx_dpm.c1520 (new_ps->dclk == old_ps->dclk))
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1537 (new_ps->dclk == old_ps->dclk))
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1805 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
1808 rps->dclk = 0;
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
[all...]
H A Dsumo_dpm.c825 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
842 (new_rps->dclk == old_rps->dclk))
860 (new_rps->dclk == old_rps->dclk))
1414 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1417 rps->dclk = 0;
1798 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1821 seq_printf(m, "uvd vclk: %d dclk
[all...]
H A Dni_dpm.c3516 (new_ps->dclk == old_ps->dclk))
3523 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3534 (new_ps->dclk == old_ps->dclk))
3541 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3903 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
3906 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
3909 rps->dclk = 0;
4286 printk("\tuvd vclk: %d dclk
[all...]
H A Drv770.c44 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) argument
53 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
55 /* bypass vclk and dclk with bclk */
60 if (!vclk || !dclk) {
66 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
H A Dkv_dpm.c836 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
842 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
851 table->entries[i].dclk, false, &dividers);
2206 pi->video_start = new_rps->dclk || new_rps->vclk ||
2580 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2583 rps->dclk = 0;
2818 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
H A Dradeon.h1329 u32 dclk; member in struct:radeon_ps
1415 u32 dclk; member in struct:radeon_uvd_clock_voltage_dependency_entry
1667 unsigned vclk, unsigned dclk,
1918 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
H A Devergreen.c1063 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) argument
1074 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
1078 cg_scratch |= (dclk / 100) << 16; /* Mhz */
1086 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) argument
1092 /* bypass vclk and dclk with bclk */
1100 if (!vclk || !dclk) {
1106 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
H A Dsi_dpm.c2275 radeon_state->vclk && radeon_state->dclk)
2927 if (rps->vclk || rps->dclk) {
5048 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5085 if (radeon_state->vclk && radeon_state->dclk) {
6202 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6205 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6208 rps->dclk = 0;
6560 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
H A Dr600.c123 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) argument
128 /* bypass vclk and dclk with bclk */
141 if (!vclk || !dclk) {
152 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
H A Dci_dpm.c2183 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
4856 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4859 rps->dclk = 0;
5291 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
H A Dr600_dpm.c1150 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
H A Dsi.c7101 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) argument
7106 /* bypass vclk and dclk with bclk */
7114 if (!vclk || !dclk) {
7120 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
H A Dbtc_dpm.c2751 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
/drivers/video/fbdev/core/
H A Dfbmon.c1092 u32 dclk; member in struct:__fb_timings
1162 * @dclk: pixelclock in Hz
1174 * where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100
1181 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) argument
1185 dclk /= 1000;
1188 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk);
1232 timings->dclk = timings->htotal * timings->hfreq;
1243 timings->dclk = timings->htotal * timings->hfreq;
1248 timings->hblank = fb_get_hblank_by_dclk(timings->dclk,
1251 timings->hfreq = timings->dclk/timing
[all...]
/drivers/mfd/
H A Dsi476x-i2c.c50 core->pinmux.dclk,
817 core->pinmux.dclk == SI476X_DCLK_DAUDIO &&
H A Dsi476x-cmd.c496 * @dclk: DCLK pin function configuration:
530 enum si476x_dclk_config dclk,
537 PIN_CFG_BYTE(dclk),
529 si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *core, enum si476x_dclk_config dclk, enum si476x_dfs_config dfs, enum si476x_dout_config dout, enum si476x_xout_config xout) argument
/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c978 int width, dclk, i, j; /*, refresh; */ local
1021 dclk = timings.Clock;
1026 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1033 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1040 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1085 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1418 /* restore extended seq regs for dclk */
1432 /* load new m, n pll values for dclk & mclk */

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