Searched refs:enable_mask (Results 1 - 25 of 88) sorted by relevance

1234

/drivers/clk/qcom/
H A Dclk-regmap.c27 * enable_reg and enable_mask fields in their struct clk_regmap and then use
41 return (val & rclk->enable_mask) == 0;
43 return (val & rclk->enable_mask) != 0;
53 * enable_reg and enable_mask fields in their struct clk_regmap and then use
64 val = rclk->enable_mask;
67 rclk->enable_mask, val);
77 * enable_reg and enable_mask fields in their struct clk_regmap and then use
86 val = rclk->enable_mask;
90 regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask,
H A Dgcc-msm8660.c53 .enable_mask = BIT(8),
128 .enable_mask = BIT(11),
144 .enable_mask = BIT(9),
179 .enable_mask = BIT(11),
195 .enable_mask = BIT(9),
230 .enable_mask = BIT(11),
246 .enable_mask = BIT(9),
281 .enable_mask = BIT(11),
297 .enable_mask = BIT(9),
332 .enable_mask
[all...]
H A Dgcc-ipq806x.c53 .enable_mask = BIT(0),
96 .enable_mask = BIT(8),
123 .enable_mask = BIT(14),
227 .enable_mask = BIT(11),
243 .enable_mask = BIT(9),
278 .enable_mask = BIT(11),
294 .enable_mask = BIT(9),
329 .enable_mask = BIT(11),
345 .enable_mask = BIT(9),
380 .enable_mask
[all...]
H A Dgcc-msm8960.c69 .enable_mask = BIT(8),
96 .enable_mask = BIT(14),
184 .enable_mask = BIT(11),
200 .enable_mask = BIT(9),
235 .enable_mask = BIT(11),
251 .enable_mask = BIT(9),
286 .enable_mask = BIT(11),
302 .enable_mask = BIT(9),
337 .enable_mask = BIT(11),
353 .enable_mask
[all...]
H A Dclk-regmap.h26 * @enable_mask: mask when using regmap enable/disable ops
27 * @enable_is_inverted: flag to indicate set enable_mask bits to disable
34 unsigned int enable_mask; member in struct:clk_regmap
H A Dmmcc-msm8974.c204 .enable_mask = BIT(0),
231 .enable_mask = BIT(1),
952 .enable_mask = BIT(0),
968 .enable_mask = BIT(0),
985 .enable_mask = BIT(0),
1001 .enable_mask = BIT(0),
1018 .enable_mask = BIT(0),
1035 .enable_mask = BIT(0),
1052 .enable_mask = BIT(0),
1069 .enable_mask
[all...]
H A Dgcc-apq8084.c126 .enable_mask = BIT(0),
189 .enable_mask = BIT(1),
216 .enable_mask = BIT(4),
288 .enable_mask = BIT(0),
305 .enable_mask = BIT(0),
1331 .enable_mask = BIT(0),
1385 .enable_mask = BIT(12),
1402 .enable_mask = BIT(17),
1418 .enable_mask = BIT(0),
1435 .enable_mask
[all...]
H A Dmmcc-apq8084.c239 .enable_mask = BIT(0),
266 .enable_mask = BIT(1),
1125 .enable_mask = BIT(0),
1140 .enable_mask = BIT(0),
1157 .enable_mask = BIT(0),
1174 .enable_mask = BIT(0),
1191 .enable_mask = BIT(0),
1208 .enable_mask = BIT(0),
1225 .enable_mask = BIT(0),
1242 .enable_mask
[all...]
H A Dmmcc-msm8960.c168 .enable_mask = BIT(2),
183 .enable_mask = BIT(0),
217 .enable_mask = BIT(2),
232 .enable_mask = BIT(0),
266 .enable_mask = BIT(2),
281 .enable_mask = BIT(0),
321 .enable_mask = BIT(2),
336 .enable_mask = BIT(0),
352 .enable_mask = BIT(8),
385 .enable_mask
[all...]
H A Dgcc-msm8974.c82 .enable_mask = BIT(0),
145 .enable_mask = BIT(1),
172 .enable_mask = BIT(4),
1047 .enable_mask = BIT(26),
1063 .enable_mask = BIT(12),
1080 .enable_mask = BIT(17),
1096 .enable_mask = BIT(0),
1113 .enable_mask = BIT(0),
1130 .enable_mask = BIT(0),
1147 .enable_mask
[all...]
/drivers/clk/mmp/
H A Dclk-apmu.c26 u32 enable_mask; member in struct:clk_apmu
39 data = readl_relaxed(apmu->base) | apmu->enable_mask;
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
70 void __iomem *base, u32 enable_mask, spinlock_t *lock)
87 apmu->enable_mask = enable_mask;
69 mmp_clk_register_apmu(const char *name, const char *parent_name, void __iomem *base, u32 enable_mask, spinlock_t *lock) argument
H A Dclk.h29 const char *parent_name, void __iomem *base, u32 enable_mask,
/drivers/regulator/
H A Drk808-regulator.c134 .enable_mask = BIT(0),
148 .enable_mask = BIT(1),
158 .enable_mask = BIT(2),
172 .enable_mask = BIT(3),
186 .enable_mask = BIT(0),
200 .enable_mask = BIT(1),
214 .enable_mask = BIT(2),
228 .enable_mask = BIT(3),
242 .enable_mask = BIT(4),
256 .enable_mask
[all...]
H A Dlp8788-ldo.c203 .enable_mask = LP8788_EN_DLDO1_M,
216 .enable_mask = LP8788_EN_DLDO2_M,
229 .enable_mask = LP8788_EN_DLDO3_M,
242 .enable_mask = LP8788_EN_DLDO4_M,
255 .enable_mask = LP8788_EN_DLDO5_M,
268 .enable_mask = LP8788_EN_DLDO6_M,
281 .enable_mask = LP8788_EN_DLDO7_M,
294 .enable_mask = LP8788_EN_DLDO8_M,
307 .enable_mask = LP8788_EN_DLDO9_M,
320 .enable_mask
[all...]
H A Dpbias-regulator.c32 u32 enable_mask; member in struct:pbias_reg_info
63 .enable_mask = BIT(1),
71 .enable_mask = BIT(9),
79 .enable_mask = BIT(26) | BIT(25) | BIT(22),
87 .enable_mask = BIT(27) | BIT(25) | BIT(26),
160 drvdata[data_idx].desc.enable_mask = info->enable_mask;
H A Dmax77686.c84 rdev->desc->enable_mask, val);
118 rdev->desc->enable_mask, val);
151 rdev->desc->enable_mask, val);
164 rdev->desc->enable_mask,
255 .enable_mask = MAX77686_OPMODE_MASK \
271 .enable_mask = MAX77686_OPMODE_MASK \
287 .enable_mask = MAX77686_OPMODE_MASK \
303 .enable_mask = MAX77686_OPMODE_MASK \
319 .enable_mask = MAX77686_OPMODE_MASK, \
334 .enable_mask
[all...]
H A Disl9305.c84 .enable_mask = ISL9305_DCD1_EN,
98 .enable_mask = ISL9305_DCD2_EN,
112 .enable_mask = ISL9305_LDO1_EN,
126 .enable_mask = ISL9305_LDO2_EN,
H A Daat2870-regulator.c38 u8 enable_mask; member in struct:aat2870_regulator
74 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask,
75 ri->enable_mask);
83 return aat2870->update(aat2870, ri->enable_addr, ri->enable_mask, 0);
97 return val & ri->enable_mask ? 1 : 0;
153 ri->enable_mask = 0x1 << ri->enable_shift;
H A Dwm8400-regulator.c128 .enable_mask = WM8400_LDO1_ENA,
142 .enable_mask = WM8400_LDO2_ENA,
156 .enable_mask = WM8400_LDO3_ENA,
170 .enable_mask = WM8400_LDO4_ENA,
184 .enable_mask = WM8400_DC1_ENA_MASK,
198 .enable_mask = WM8400_DC1_ENA_MASK,
/drivers/tty/
H A Dsysrq.c100 .enable_mask = SYSRQ_ENABLE_LOG,
113 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
129 .enable_mask = SYSRQ_ENABLE_KEYBOARD,
147 .enable_mask = SYSRQ_ENABLE_DUMP,
160 .enable_mask = SYSRQ_ENABLE_BOOT,
171 .enable_mask = SYSRQ_ENABLE_SYNC,
193 .enable_mask = SYSRQ_ENABLE_REMOUNT,
257 .enable_mask = SYSRQ_ENABLE_DUMP,
272 .enable_mask = SYSRQ_ENABLE_DUMP,
283 .enable_mask
1028 sysrq_toggle_support(int enable_mask) argument
[all...]
/drivers/clk/ti/
H A Dapll.c61 v &= ~ad->enable_mask;
62 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
100 v &= ~ad->enable_mask;
101 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
114 v &= ad->enable_mask;
116 v >>= __ffs(ad->enable_mask);
210 ad->enable_mask = 0x3;
233 v &= ad->enable_mask;
235 v >>= __ffs(ad->enable_mask);
259 v &= ~ad->enable_mask;
[all...]
H A Ddpll.c340 .enable_mask = 0x7,
360 .enable_mask = 0x7,
379 .enable_mask = 0x7 << 16,
399 .enable_mask = 0x7 << 16,
422 .enable_mask = 0x7,
441 .enable_mask = 0x7,
462 .enable_mask = 0x7,
483 .enable_mask = 0x7,
504 .enable_mask = 0x7,
526 .enable_mask
[all...]
/drivers/acpi/acpica/
H A Dhwgpe.c96 u32 enable_mask; local
110 status = acpi_hw_read(&enable_mask, &gpe_register_info->enable_address);
131 ACPI_SET_BIT(enable_mask, register_bit);
136 ACPI_CLEAR_BIT(enable_mask, register_bit);
147 status = acpi_hw_write(enable_mask, &gpe_register_info->enable_address);
/drivers/clk/
H A Dclk-palmas.c37 unsigned int enable_mask; member in struct:palmas_clk32k_desc
70 cinfo->clk_desc->enable_mask,
71 cinfo->clk_desc->enable_mask);
95 cinfo->clk_desc->enable_mask, 0);
117 return !!(val & cinfo->clk_desc->enable_mask);
141 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
157 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
/drivers/clocksource/
H A Dtime-armada-370-xp.c79 static u32 enable_mask; variable
119 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
138 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
237 enable_mask = TIMER0_EN;
240 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
261 TIMER0_RELOAD_EN | enable_mask,
262 TIMER0_RELOAD_EN | enable_mask);

Completed in 282 milliseconds

1234