Searched refs:pe (Results 1 - 25 of 48) sorted by relevance

12

/drivers/scsi/libsas/
H A Dsas_dump.h27 void sas_dprint_porte(int phyid, enum port_event pe);
28 void sas_dprint_phye(int phyid, enum phy_event pe);
H A Dsas_dump.c47 void sas_dprint_porte(int phyid, enum port_event pe) argument
49 SAS_DPRINTK("phy%d: port event: %s\n", phyid, sas_porte_str[pe]);
51 void sas_dprint_phye(int phyid, enum phy_event pe) argument
53 SAS_DPRINTK("phy%d: phy event: %s\n", phyid, sas_phye_str[pe]);
/drivers/vfio/
H A Dvfio_spapr_eeh.c37 struct eeh_pe *pe; local
50 pe = eeh_iommu_group_to_pe(group);
51 if (!pe)
62 ret = eeh_pe_set_option(pe, EEH_OPT_DISABLE);
65 ret = eeh_pe_set_option(pe, EEH_OPT_ENABLE);
68 ret = eeh_pe_set_option(pe, EEH_OPT_THAW_MMIO);
71 ret = eeh_pe_set_option(pe, EEH_OPT_THAW_DMA);
74 ret = eeh_pe_get_state(pe);
77 ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE);
80 ret = eeh_pe_reset(pe, EEH_RESET_HO
[all...]
/drivers/net/ethernet/marvell/
H A Dmvpp2.c989 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) argument
993 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
997 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1000 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1002 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1005 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1007 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1013 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) argument
1017 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1021 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe
1064 mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) argument
1073 mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, unsigned int port, bool add) argument
1085 mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, unsigned int ports) argument
1097 mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) argument
1105 mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, unsigned int offs, unsigned char byte, unsigned char enable) argument
1114 mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, unsigned int offs, unsigned char *byte, unsigned char *enable) argument
1123 mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, u16 data) argument
1136 mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, unsigned int bits, unsigned int enable) argument
1156 mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) argument
1162 mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, unsigned short ethertype) argument
1170 mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, int val) argument
1177 mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, int val) argument
1184 mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, unsigned int bits, unsigned int mask) argument
1205 mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) argument
1211 mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, unsigned int bits, unsigned int mask) argument
1232 mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) argument
1248 mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) argument
1261 mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, unsigned int op) argument
1288 mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, unsigned int type, int offset, unsigned int op) argument
1337 struct mvpp2_prs_entry *pe; local
1389 struct mvpp2_prs_entry pe; local
1424 struct mvpp2_prs_entry pe; local
1466 struct mvpp2_prs_entry pe; local
1515 struct mvpp2_prs_entry pe; local
1574 struct mvpp2_prs_entry pe; local
1643 struct mvpp2_prs_entry *pe; local
1693 struct mvpp2_prs_entry *pe; local
1786 struct mvpp2_prs_entry *pe; local
1827 struct mvpp2_prs_entry *pe; local
1907 struct mvpp2_prs_entry pe; local
1970 struct mvpp2_prs_entry pe; local
2022 struct mvpp2_prs_entry pe; local
2062 struct mvpp2_prs_entry pe; local
2129 struct mvpp2_prs_entry pe; local
2153 struct mvpp2_prs_entry pe; local
2176 struct mvpp2_prs_entry pe; local
2206 struct mvpp2_prs_entry pe; local
2260 struct mvpp2_prs_entry pe; local
2487 struct mvpp2_prs_entry pe; local
2562 struct mvpp2_prs_entry pe; local
2673 struct mvpp2_prs_entry pe; local
2756 struct mvpp2_prs_entry pe; local
2955 mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, const u8 *da, unsigned char *mask) argument
2978 struct mvpp2_prs_entry *pe; local
3013 struct mvpp2_prs_entry *pe; local
3129 struct mvpp2_prs_entry pe; local
3209 struct mvpp2_prs_entry *pe; local
[all...]
/drivers/net/wireless/ath/ath9k/
H A Ddfs.c53 struct pulse_event *pe)
123 pe->width = dur_to_usecs(sc->sc_ah, dur);
124 pe->rssi = rssi;
141 struct pulse_event pe; local
177 pe.freq = ah->curchan->channel;
178 pe.ts = mactime;
179 if (ath9k_postprocess_radar_event(sc, &ard, &pe)) {
184 pe.freq, pe.ts, pe
51 ath9k_postprocess_radar_event(struct ath_softc *sc, struct ath_radar_data *ard, struct pulse_event *pe) argument
[all...]
/drivers/staging/speakup/
H A Dselection.c56 int i, ps, pe; local
64 pe = spk_ye * vc->vc_size_row + (spk_xe << 1);
66 if (ps > pe) {
70 ps = pe;
71 pe = tmp;
83 new_sel_end = pe;
89 for (pe = new_sel_end + 2; ; pe += 2)
90 if (!ishardspace(sel_pos(pe)) ||
91 atedge(pe, v
[all...]
/drivers/tty/vt/
H A Dselection.c164 int i, ps, pe, multiplier; local
185 pe = ye * vc->vc_size_row + (xe << 1);
199 if (ps > pe) /* make sel_start <= sel_end */
202 ps = pe;
203 pe = tmp;
220 new_sel_end = pe;
233 spc = isspace(sel_pos(pe));
234 for (new_sel_end = pe; ; pe += 2)
236 if ((spc && !isspace(sel_pos(pe))) ||
[all...]
/drivers/clk/st/
H A Dclkgen-fsyn.c39 unsigned long pe; member in struct:stm_fs
45 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */
46 { .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */
47 { .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */
48 { .mdiv = 0x13, .pe = 0x0, .sdiv = 0x2, .nsdiv = 1 }, /* 48 MHz */
49 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */
53 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
54 { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
55 { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */
56 { .mdiv = 0x11, .pe
135 struct clkgen_field pe[QUADFS_MAX_CHAN]; member in struct:clkgen_quadfs_data
699 u32 pe; member in struct:st_clk_quadfs_fsynth
[all...]
/drivers/md/
H A Ddm-cache-policy-cleaner.c172 static int wb_map(struct dm_cache_policy *pe, dm_oblock_t oblock, argument
176 struct policy *p = to_policy(pe);
200 static int wb_lookup(struct dm_cache_policy *pe, dm_oblock_t oblock, dm_cblock_t *cblock) argument
203 struct policy *p = to_policy(pe);
223 static void __set_clear_dirty(struct dm_cache_policy *pe, dm_oblock_t oblock, bool set) argument
225 struct policy *p = to_policy(pe);
246 static void wb_set_dirty(struct dm_cache_policy *pe, dm_oblock_t oblock) argument
248 struct policy *p = to_policy(pe);
252 __set_clear_dirty(pe, oblock, true);
256 static void wb_clear_dirty(struct dm_cache_policy *pe, dm_oblock_ argument
275 wb_load_mapping(struct dm_cache_policy *pe, dm_oblock_t oblock, dm_cblock_t cblock, uint32_t hint, bool hint_valid) argument
296 wb_destroy(struct dm_cache_policy *pe) argument
316 wb_remove_mapping(struct dm_cache_policy *pe, dm_oblock_t oblock) argument
330 wb_force_mapping(struct dm_cache_policy *pe, dm_oblock_t current_oblock, dm_oblock_t oblock) argument
359 wb_writeback_work(struct dm_cache_policy *pe, dm_oblock_t *oblock, dm_cblock_t *cblock) argument
382 wb_residency(struct dm_cache_policy *pe) argument
[all...]
H A Ddm-snap.c631 struct dm_snap_pending_exception *pe = mempool_alloc(s->pending_pool, local
635 pe->snap = s;
637 return pe;
640 static void free_pending_exception(struct dm_snap_pending_exception *pe) argument
642 struct dm_snapshot *s = pe->snap;
644 mempool_free(pe, s->pending_pool);
1383 static void pending_complete(struct dm_snap_pending_exception *pe, int success) argument
1386 struct dm_snapshot *s = pe->snap;
1407 *e = pe->e;
1417 __check_for_conflicting_io(s, pe
1457 struct dm_snap_pending_exception *pe = context; local
1462 complete_exception(struct dm_snap_pending_exception *pe) argument
1481 struct dm_snap_pending_exception *pe = context; local
1515 start_copy(struct dm_snap_pending_exception *pe) argument
1543 start_full_bio(struct dm_snap_pending_exception *pe, struct bio *bio) argument
1582 __find_pending_exception(struct dm_snapshot *s, struct dm_snap_pending_exception *pe, chunk_t chunk) argument
1627 struct dm_snap_pending_exception *pe = NULL; local
1976 struct dm_snap_pending_exception *pe; local
[all...]
/drivers/gpu/drm/radeon/
H A Dsi_dma.c63 * @pe: addr of the page entry
71 uint64_t pe, uint64_t src,
81 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
83 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
86 pe += bytes;
97 * @pe: addr of the page entry
98 * @addr: dst addr to write into pe
107 uint64_t pe,
121 ib->ptr[ib->length_dw++] = pe;
122 ib->ptr[ib->length_dw++] = upper_32_bits(pe)
69 si_dma_vm_copy_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t src, unsigned count) argument
105 si_dma_vm_write_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) argument
153 si_dma_vm_set_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) argument
[all...]
H A Dni_dma.c308 * @pe: addr of the page entry
316 uint64_t pe, uint64_t src,
328 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
330 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
333 pe += ndw * 4;
344 * @pe: addr of the page entry
345 * @addr: dst addr to write into pe
354 uint64_t pe,
369 ib->ptr[ib->length_dw++] = pe;
370 ib->ptr[ib->length_dw++] = upper_32_bits(pe)
314 cayman_dma_vm_copy_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t src, unsigned count) argument
352 cayman_dma_vm_write_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) argument
401 cayman_dma_vm_set_pages(struct radeon_device *rdev, struct radeon_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags) argument
[all...]
H A Dradeon_trace.h84 TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
86 TP_ARGS(pe, addr, count, incr, flags),
88 __field(u64, pe)
96 __entry->pe = pe;
102 TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u",
103 __entry->pe, __entry->addr, __entry->incr,
/drivers/gpu/drm/nouveau/core/include/subdev/bios/
H A Ddp.h22 u8 pe; member in struct:nvbios_dpcfg
31 nvbios_dpcfg_match(struct nouveau_bios *, u16 outp, u8 pc, u8 vs, u8 pe,
/drivers/isdn/hardware/eicon/
H A Ddivasproc.c359 struct proc_dir_entry *de, *pe; local
367 pe = proc_create_data(info_proc_name, S_IRUGO | S_IWUSR, de,
369 if (!pe)
371 a->proc_info = (void *) pe;
373 pe = proc_create_data(grp_opt_proc_name, S_IRUGO | S_IWUSR, de,
375 if (pe)
376 a->proc_grp_opt = (void *) pe;
377 pe = proc_create_data(d_l1_down_proc_name, S_IRUGO | S_IWUSR, de,
379 if (pe)
380 a->proc_d_l1_down = (void *) pe;
[all...]
/drivers/gpu/drm/nouveau/core/subdev/bios/
H A Ddp.c170 info->pe = nv_ro08(bios, data + 0x03);
177 info->pe = nv_ro08(bios, data + 0x02);
189 nvbios_dpcfg_match(struct nouveau_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe, argument
198 idx = (pc * 10) + vsoff[vs] + pe;
203 nv_ro08(bios, data + 0x01) == pe)
/drivers/gpu/drm/nouveau/core/engine/disp/
H A Dsornv94.c105 nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) argument
122 addr = nvbios_dpcfg_match(bios, addr, 0, vs, pe,
133 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
H A Dsornvd0.c83 nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) argument
100 addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
111 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
H A Doutpdp.h57 int (*drv_ctl)(struct nvkm_output_dp *, int ln, int vs, int pe, int pc);
/drivers/misc/cxl/
H A Dcontext.c94 ctx->pe = i;
123 pr_devel("%s: mmio physical: %llx pe: %i master:%i\n", __func__,
124 ctx->psn_phys, ctx->pe , ctx->master);
184 idr_remove(&ctx->afu->contexts_idr, ctx->pe);
H A Dfile.c83 pr_devel("afu_open pe: %i\n", ctx->pe);
112 pr_devel("%s: closing cxl file descriptor. pe: %i\n",
113 __func__, ctx->pe);
137 pr_devel("%s: pe: %i\n", __func__, ctx->pe);
196 pr_devel("%s: pe: %i\n", __func__, ctx->pe);
198 if (copy_to_user(upe, &ctx->pe, sizeof(__u32)))
247 pr_devel("afu_poll wait done pe
[all...]
H A Dfault.c118 pr_devel("CXL interrupt: Segment fault pe: %i ea: %#llx\n", ctx->pe, ea);
156 pr_devel("Page fault successfully handled for pe: %i!\n", ctx->pe);
171 cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) != ctx->pe) {
179 pr_devel("CXL BOTTOM HALF handling fault for afu pe: %i. "
180 "DSISR: %#llx DAR: %#llx\n", ctx->pe, dsisr, dar);
H A Dnative.c285 *(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
287 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
295 (cmd | (cmd >> 16) | ctx->pe))
315 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
318 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
332 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
336 pr_devel("%s Terminate pe
[all...]
/drivers/net/wireless/ath/
H A Ddfs_pri_detector.c116 static void pool_put_pulse_elem(struct pulse_elem *pe) argument
119 list_add(&pe->head, &pulse_pool);
147 struct pulse_elem *pe = NULL; local
150 pe = list_first_entry(&pulse_pool, struct pulse_elem, head);
151 list_del(&pe->head);
155 return pe;
H A Ddfs_pattern_detector.h91 struct pulse_event *pe);

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