Searched refs:pgd (Results 1 - 18 of 18) sorted by relevance

/drivers/gpu/drm/nouveau/core/engine/fifo/
H A Dnv50.h15 struct nouveau_gpuobj *pgd; member in struct:nv50_fifo_base
H A Dnvc0.c64 struct nouveau_gpuobj *pgd; member in struct:nvc0_fifo_base
338 &base->pgd);
342 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
343 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
347 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
358 nouveau_vm_ref(NULL, &base->vm, base->pgd);
359 nouveau_gpuobj_ref(NULL, &base->pgd);
H A Dnv50.c421 &base->pgd);
425 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
436 nouveau_vm_ref(NULL, &base->vm, base->pgd);
437 nouveau_gpuobj_ref(NULL, &base->pgd);
H A Dnve0.c83 struct nouveau_gpuobj *pgd; member in struct:nve0_fifo_base
371 &base->pgd);
375 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
376 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
380 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
391 nouveau_vm_ref(NULL, &base->vm, base->pgd);
392 nouveau_gpuobj_ref(NULL, &base->pgd);
H A Dnv84.c377 0, &base->pgd);
381 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
/drivers/gpu/drm/nouveau/core/subdev/bar/
H A Dnvc0.c35 struct nouveau_gpuobj *pgd; member in struct:nvc0_bar_priv_vm
98 &bar_vm->pgd);
123 ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
128 nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
129 nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
177 nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
178 nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
183 nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
185 nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
H A Dnv50.c38 struct nouveau_gpuobj *pgd; member in struct:nv50_bar_priv
136 0, &priv->pgd);
157 ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd);
184 ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
218 nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
222 nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
224 nouveau_gpuobj_ref(NULL, &priv->pgd);
/drivers/iommu/
H A Dipmmu-vmsa.c44 pgd_t *pgd; member in struct:ipmmu_vmsa_domain
336 ipmmu_flush_pgtable(domain->mmu, domain->pgd,
337 IPMMU_PTRS_PER_PGD * sizeof(*domain->pgd));
338 ttbr = __pa(domain->pgd);
495 pgd_t *pgd, *pgd_base = domain->pgd; local
504 pgd = pgd_base;
506 if (pgd_none(*pgd))
508 ipmmu_free_pmds((pud_t *)pgd);
509 pgd
539 ipmmu_alloc_pmd(struct ipmmu_vmsa_device *mmu, pgd_t *pgd, unsigned long iova) argument
630 pgd_t *pgd = domain->pgd; local
781 pgd_t *pgd = domain->pgd; local
970 pgd_t pgd; local
[all...]
H A Darm-smmu.c400 pgd_t *pgd; member in struct:arm_smmu_cfg
820 arm_smmu_flush_pgtable(smmu, cfg->pgd,
822 reg = __pa(cfg->pgd);
824 reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
984 pgd_t *pgd; local
995 pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
996 if (!pgd)
998 smmu_domain->cfg.pgd = pgd;
1033 static void arm_smmu_free_puds(pgd_t *pgd) argument
1054 pgd_t *pgd, *pgd_base = cfg->pgd; local
1417 arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, unsigned long addr, unsigned long end, phys_addr_t phys, int prot, int stage) argument
1459 pgd_t *pgd = cfg->pgd; local
1530 pgd_t *pgdp, pgd; local
[all...]
H A Domap-iommu.c564 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
699 * @ppgd: iommu pgd entry pointer to be returned
839 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
846 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
1208 u32 *pgd, *pte; local
1211 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1222 if (iopgd_is_section(*pgd))
[all...]
H A Dintel-iommu.c347 struct dma_pte *pgd; /* virtual address */ member in struct:dmar_domain
843 BUG_ON(!domain->pgd);
849 parent = domain->pgd;
900 parent = domain->pgd;
1001 domain->pgd, 0, start_pfn, last_pfn);
1003 /* free pgd */
1005 free_pgtable_page(domain->pgd);
1006 domain->pgd = NULL;
1104 domain->pgd, 0, start_pfn, last_pfn, NULL);
1106 /* free pgd */
1785 struct dma_pte *pgd; local
[all...]
H A Damd_iommu_v2.c458 __pa(pasid_state->mm->pgd));
683 __pa(pasid_state->mm->pgd));
H A Dexynos-iommu.c280 phys_addr_t pgd)
282 __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
279 __sysmmu_set_ptbase(void __iomem *sfrbase, phys_addr_t pgd) argument
/drivers/gpu/drm/nouveau/core/subdev/vm/
H A Dbase.c402 nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) argument
408 if (!pgd)
415 nouveau_gpuobj_ref(pgd, &vpgd->obj);
419 vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
430 struct nouveau_gpuobj *pgd = NULL; local
438 pgd = vpgd->obj;
446 nouveau_gpuobj_ref(NULL, &pgd);
466 struct nouveau_gpuobj *pgd)
469 int ret = nouveau_vm_link(ref, pgd);
477 nouveau_vm_unlink(*ptr, pgd);
465 nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, struct nouveau_gpuobj *pgd) argument
[all...]
H A Dnv50.c38 nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, argument
62 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
63 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
H A Dnvc0.c80 nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, argument
90 nv_wo32(pgd, (index * 8) + 0, pde[0]);
91 nv_wo32(pgd, (index * 8) + 4, pde[1]);
/drivers/gpu/drm/nouveau/core/include/subdev/
H A Dvm.h80 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
126 struct nouveau_gpuobj *pgd);
/drivers/lguest/x86/
H A Dcore.c102 pages->state.host_cr3 = __pa(current->mm->pgd);

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