1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <core/gpuobj.h>
26
27#include <subdev/timer.h>
28#include <subdev/fb.h>
29#include <subdev/vm.h>
30
31#include "priv.h"
32
33struct nvc0_bar_priv_vm {
34	struct nouveau_gpuobj *mem;
35	struct nouveau_gpuobj *pgd;
36	struct nouveau_vm *vm;
37};
38
39struct nvc0_bar_priv {
40	struct nouveau_bar base;
41	spinlock_t lock;
42	struct nvc0_bar_priv_vm bar[2];
43};
44
45static int
46nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
47	      u32 flags, struct nouveau_vma *vma)
48{
49	struct nvc0_bar_priv *priv = (void *)bar;
50	int ret;
51
52	ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
53	if (ret)
54		return ret;
55
56	nouveau_vm_map(vma, mem);
57	return 0;
58}
59
60static int
61nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
62	      u32 flags, struct nouveau_vma *vma)
63{
64	struct nvc0_bar_priv *priv = (void *)bar;
65	int ret;
66
67	ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
68			     mem->page_shift, flags, vma);
69	if (ret)
70		return ret;
71
72	nouveau_vm_map(vma, mem);
73	return 0;
74}
75
76static void
77nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
78{
79	nouveau_vm_unmap(vma);
80	nouveau_vm_put(vma);
81}
82
83static int
84nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm,
85		 int bar_nr)
86{
87	struct nouveau_device *device = nv_device(&priv->base);
88	struct nouveau_vm *vm;
89	resource_size_t bar_len;
90	int ret;
91
92	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
93				&bar_vm->mem);
94	if (ret)
95		return ret;
96
97	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
98				&bar_vm->pgd);
99	if (ret)
100		return ret;
101
102	bar_len = nv_device_resource_len(device, bar_nr);
103
104	ret = nouveau_vm_new(device, 0, bar_len, 0, &vm);
105	if (ret)
106		return ret;
107
108	atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
109
110	/*
111	 * Bootstrap page table lookup.
112	 */
113	if (bar_nr == 3) {
114		ret = nouveau_gpuobj_new(nv_object(priv), NULL,
115					 (bar_len >> 12) * 8, 0x1000,
116					 NVOBJ_FLAG_ZERO_ALLOC,
117					&vm->pgt[0].obj[0]);
118		vm->pgt[0].refcount[0] = 1;
119		if (ret)
120			return ret;
121	}
122
123	ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
124	nouveau_vm_ref(NULL, &vm, NULL);
125	if (ret)
126		return ret;
127
128	nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
129	nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
130	nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
131	nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
132
133	return 0;
134}
135
136int
137nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
138	      struct nouveau_oclass *oclass, void *data, u32 size,
139	      struct nouveau_object **pobject)
140{
141	struct nouveau_device *device = nv_device(parent);
142	struct nvc0_bar_priv *priv;
143	bool has_bar3 = nv_device_resource_len(device, 3) != 0;
144	int ret;
145
146	ret = nouveau_bar_create(parent, engine, oclass, &priv);
147	*pobject = nv_object(priv);
148	if (ret)
149		return ret;
150
151	/* BAR3 */
152	if (has_bar3) {
153		ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
154		if (ret)
155			return ret;
156		priv->base.alloc = nouveau_bar_alloc;
157		priv->base.kmap = nvc0_bar_kmap;
158	}
159
160	/* BAR1 */
161	ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1);
162	if (ret)
163		return ret;
164
165	priv->base.umap = nvc0_bar_umap;
166	priv->base.unmap = nvc0_bar_unmap;
167	priv->base.flush = nv84_bar_flush;
168	spin_lock_init(&priv->lock);
169	return 0;
170}
171
172void
173nvc0_bar_dtor(struct nouveau_object *object)
174{
175	struct nvc0_bar_priv *priv = (void *)object;
176
177	nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
178	nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
179	nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
180
181	if (priv->bar[0].vm) {
182		nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
183		nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
184	}
185	nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
186	nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
187
188	nouveau_bar_destroy(&priv->base);
189}
190
191int
192nvc0_bar_init(struct nouveau_object *object)
193{
194	struct nvc0_bar_priv *priv = (void *)object;
195	int ret;
196
197	ret = nouveau_bar_init(&priv->base);
198	if (ret)
199		return ret;
200
201	nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
202	nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
203
204	nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
205	if (priv->bar[0].mem)
206		nv_wr32(priv, 0x001714,
207			0xc0000000 | priv->bar[0].mem->addr >> 12);
208	return 0;
209}
210
211struct nouveau_oclass
212nvc0_bar_oclass = {
213	.handle = NV_SUBDEV(BAR, 0xc0),
214	.ofuncs = &(struct nouveau_ofuncs) {
215		.ctor = nvc0_bar_ctor,
216		.dtor = nvc0_bar_dtor,
217		.init = nvc0_bar_init,
218		.fini = _nouveau_bar_fini,
219	},
220};
221