Searched refs:pllctrl (Results 1 - 3 of 3) sorted by relevance
/drivers/gpu/drm/sti/ |
H A D | sti_hdmi_tx3g4c28phy.c | 77 u32 val, tmdsck, idf, odf, pllctrl = 0; local 101 pllctrl |= 40 << PLL_CFG_NDIV_SHIFT; 108 pllctrl |= idf << PLL_CFG_IDF_SHIFT; 109 pllctrl |= odf << PLL_CFG_ODF_SHIFT; 115 DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl); 116 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG);
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H A D | sti_hdmi_tx3g0c55phy.c | 205 u32 val, tmdsck, freqvco, pllctrl = 0; local 215 pllctrl = 2 << HDMI_SRZ_PLL_CFG_NDIV_SHIFT; 225 pllctrl |= HDMI_SRZ_PLL_CFG_MODE(pllmodes[i].mode); 230 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_425MHZ); 232 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_850MHZ); 234 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_1700MHZ); 236 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_3000MHZ); 246 DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl); 247 hdmi_write(hdmi, pllctrl, HDMI_SRZ_PLL_CF [all...] |
/drivers/clk/keystone/ |
H A D | pll.c | 87 * get bits 0-5 of multiplier from pllctrl PLLM register 154 * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of 157 static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) argument 187 pll_data->has_pllctrl = pllctrl;
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