Searched refs:bypass (Results 1 - 25 of 26) sorted by relevance

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/drivers/regulator/
H A Dinternal.h28 unsigned int bypass:1; member in struct:regulator
H A Danatop-regulator.c54 bool bypass; member in struct:anatop_regulator
89 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
109 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
124 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
137 WARN_ON(!anatop_reg->bypass);
139 WARN_ON(anatop_reg->bypass);
141 *enable = anatop_reg->bypass;
150 if (enable == anatop_reg->bypass)
154 anatop_reg->bypass = enable;
284 sreg->bypass
[all...]
H A Dcore.c418 label = "bypass";
618 bool bypass; local
621 ret = rdev->desc->ops->get_bypass(rdev, &bypass);
625 else if (bypass)
632 static DEVICE_ATTR(bypass, 0444,
3083 * regulator_allow_bypass - allow the regulator to go into bypass mode
3086 * @enable: enable or disable bypass mode
3088 * Allow the regulator to go into bypass mode if all other consumers
3089 * for the regulator also enable bypass mode and the machine
3107 if (enable && !regulator->bypass) {
[all...]
/drivers/md/bcache/
H A Drequest.h19 unsigned bypass:1; member in struct:data_insert_op::__anon1972::__anon1973
H A Dstats.c184 bool hit, bool bypass)
186 if (!bypass)
199 bool hit, bool bypass)
202 mark_cache_stats(&dc->accounting.collector, hit, bypass);
203 mark_cache_stats(&c->accounting.collector, hit, bypass);
183 mark_cache_stats(struct cache_stat_collector *stats, bool hit, bool bypass) argument
198 bch_mark_cache_accounting(struct cache_set *c, struct bcache_device *d, bool hit, bool bypass) argument
H A Drequest.c201 if (op->bypass)
274 op->bypass = true;
307 * If s->bypass is true, instead of inserting the data it invalidates the
315 op->writeback, op->bypass);
770 !s->cache_miss, s->iop.bypass);
771 trace_bcache_read(s->orig_bio, !s->cache_miss, s->iop.bypass);
789 if (s->cache_miss || s->iop.bypass) {
887 s->iop.bypass = false;
899 s->iop.bypass = true;
903 s->iop.bypass)) {
[all...]
/drivers/clk/socfpga/
H A Dclk-pll.c27 /* Clock bypass bits */
55 unsigned long bypass; local
58 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
59 if (bypass & MAINPLL_BYPASS)
/drivers/clk/at91/
H A Dclk-slow.c125 bool bypass)
148 if (bypass)
166 bool bypass; local
171 bypass = of_property_read_bool(np, "atmel,osc-bypass");
174 bypass);
121 at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const char *parent_name, unsigned long startup, bool bypass) argument
H A Dclk-main.c146 bool bypass)
177 if (bypass)
199 bool bypass; local
202 bypass = of_property_read_bool(np, "atmel,osc-bypass");
209 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
142 at91_clk_register_main_osc(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name, bool bypass) argument
/drivers/base/regmap/
H A Dregcache.c299 unsigned int bypass; local
304 /* Remember the initial bypass state */
305 bypass = map->cache_bypass;
337 /* Restore the bypass state */
339 map->cache_bypass = bypass;
367 unsigned int bypass; local
373 /* Remember the initial bypass state */
374 bypass = map->cache_bypass;
392 /* Restore the bypass state */
393 map->cache_bypass = bypass;
[all...]
H A Dregmap.c1971 bool bypass; local
1975 bypass = map->cache_bypass;
1980 map->cache_bypass = bypass;
2564 bool bypass; local
2583 bypass = map->cache_bypass;
2594 map->cache_bypass = bypass;
/drivers/crypto/amcc/
H A Dcrypto4xx_core.h130 u32 bypass; member in struct:crypto4xx_ctx
H A Dcrypto4xx_reg_def.h266 u32 bypass:8; member in struct:ce_pd_ctl_len::__anon497
H A Dcrypto4xx_core.c981 pd->pd_ctl_len.w = 0x00400000 | (ctx->bypass << 24) | datalen;
/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dnva3.c347 u32 bypass; local
351 bypass = nv_rd32(priv, ctrl) & 0x00000008;
352 if (!bypass) {
/drivers/media/usb/dvb-usb/
H A Dvp702x.c155 static int vp702x_set_pld_mode(struct dvb_usb_adapter *adap, u8 bypass) argument
166 ret = vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e,
231 vp702x_set_pld_mode(adap, 1); /* bypass */
/drivers/irqchip/
H A Dirq-gic.c358 u32 bypass = 0; local
361 * Preserve bypass disable bits to be written back later
363 bypass = readl(cpu_base + GIC_CPU_CTRL);
364 bypass &= GICC_DIS_BYPASS_MASK;
366 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
/drivers/media/platform/exynos4-is/
H A Dfimc-is-param.c467 drc->control.bypass = val;
689 isp->control.bypass = CONTROL_BYPASS_DISABLE;
861 fd->control.bypass = CONTROL_BYPASS_DISABLE;
H A Dfimc-is-param.h454 u32 bypass; member in struct:param_control
/drivers/staging/media/davinci_vpfe/
H A Ddm365_resizer.c106 resizer_configure_passthru(struct vpfe_resizer_device *resizer, int bypass) argument
125 if (bypass) {
534 param->rsz_common.passthrough = cont_config->bypass;
535 if (cont_config->bypass)
795 param->rsz_common.passthrough = config->bypass;
796 if (config->bypass)
H A Ddavinci_vpfe_user.h915 * 1 - bypass Gamma correction. Data is divided by 16
919 * 1 - bypass Gamma correction. Data is divided by 16
923 * 1 - bypass Gamma correction. Data is divided by 16
1282 unsigned char bypass; member in struct:vpfe_rsz_config_params
/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c103 * @bypass: unused scaler path.
111 bool bypass; member in struct:fimc_scaler
123 * @bypass: scaler bypass mode.
132 u32 bypass; member in struct:fimc_capability
429 /* bypass */
738 /* bypass */
778 /* bypass */
1024 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1025 sc->range, sc->bypass, s
[all...]
/drivers/mfd/
H A Darizona-core.c924 !arizona->pdata.micbias[i].bypass)
927 /* Apply default for bypass mode */
944 if (arizona->pdata.micbias[i].bypass)
/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4.h309 unsigned char bypass; member in struct:adapter_params
905 return adap->params.bypass;
/drivers/infiniband/hw/cxgb3/
H A Dcxio_wr.h402 struct t3_bypass_wr bypass; member in union:t3_wr

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