/drivers/gpu/drm/msm/mdp/mdp4/ |
H A D | mdp4.xml.h | 339 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } argument 341 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } argument 361 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } argument 363 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } argument 365 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } argument 367 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) argument 369 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) argument 371 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) argument 383 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) argument 385 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) argument 401 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) argument 403 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) argument 405 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) argument 407 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) argument 409 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) argument 411 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) argument 413 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) argument 415 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) argument 417 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) argument 419 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) argument 425 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) argument 427 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) argument 556 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) argument 558 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) argument 560 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) argument 562 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) argument 564 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) argument 566 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) argument 568 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) argument 570 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) argument 572 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) argument 574 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) argument 775 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) argument 777 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 779 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) argument 781 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 783 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) argument 785 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 787 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) argument 789 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) argument 791 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) argument 793 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) argument [all...] |
/drivers/video/fbdev/ |
H A D | c2p_core.h | 20 static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, argument 23 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; 25 d[i1] ^= t;
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/drivers/gpu/drm/msm/mdp/mdp5/ |
H A D | mdp5.xml.h | 294 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } argument 296 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } argument 333 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } argument 335 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } argument 797 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; } argument 799 REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) argument 821 REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) argument 823 REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) argument 825 REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) argument 827 REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) argument 829 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) argument 831 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) argument 833 REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) argument 835 REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) argument 837 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) argument 839 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) argument [all...] |
/drivers/isdn/mISDN/ |
H A D | l1oip_codec.c | 326 int i1, i2, c, sample; local 340 i1 = 0; 341 while (i1 < 256) { 343 c = ulaw_to_4bit[i1]; 345 c = alaw_to_4bit[i1]; 348 table_com[(i1 << 8) | i2] |= (c << 4); 349 table_com[(i2 << 8) | i1] |= c; 352 i1++; 356 i1 = 0; 357 while (i1 < 1 [all...] |
H A D | dsp_cmx.c | 388 int memb = 0, i, ii, i1, i2; local 858 i1 = 0; 860 while (i1 < ii) { 861 if (freeslots[i1]) 863 i1++; 865 if (i1 == ii) { 875 i2 = i1 + 1; 893 member->dsp->pcm_slot_tx = i1; 896 nextm->dsp->pcm_slot_rx = i1;
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/drivers/connector/ |
H A D | cn_queue.c | 68 int cn_cb_equal(struct cb_id *i1, struct cb_id *i2) argument 70 return ((i1->idx == i2->idx) && (i1->val == i2->val));
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/drivers/gpu/drm/vmwgfx/ |
H A D | vmwgfx_context.c | 565 cmd->body.type = bi->i1.shader_type; 598 cmd->body.type = bi->i1.rt_type; 639 cmd->body.s1.stage = bi->i1.texture_stage; 681 if (unlikely((unsigned)bi->i1.rt_type >= SVGA3D_RT_MAX)) { 683 (unsigned) bi->i1.rt_type); 686 loc = &cbs->render_targets[bi->i1.rt_type]; 689 if (unlikely((unsigned)bi->i1.texture_stage >= 692 (unsigned) bi->i1.texture_stage); 695 loc = &cbs->texture_units[bi->i1.texture_stage]; 698 if (unlikely((unsigned)bi->i1 [all...] |
H A D | vmwgfx_execbuf.c | 659 bi.i1.rt_type = cmd->body.type; 1376 bi.i1.texture_stage = cur_state->stage; 1780 bi.i1.shader_type = cmd->body.type;
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H A D | vmwgfx_drv.h | 283 * @i1: Union of information needed to unbind. 294 } i1; member in struct:vmw_ctx_bindinfo
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/drivers/char/hw_random/ |
H A D | n2-asm.S | 31 mov %i1, %o1
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/drivers/block/ |
H A D | umem.c | 194 int i, i1; local 200 for (i1 = 0; i1 < 16; i1++)
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/drivers/staging/lustre/lustre/llite/ |
H A D | llite_lib.c | 2244 struct inode *i1, struct inode *i2, 2248 LASSERT(i1 != NULL); 2250 if (namelen > ll_i2sbi(i1)->ll_namelen) 2259 ll_i2gids(op_data->op_suppgids, i1, i2); 2260 op_data->op_fid1 = *ll_inode2fid(i1); 2261 op_data->op_capa1 = ll_mdscapa_get(i1); 2290 if (opc == LUSTRE_OPC_CREATE && i1 == i2 && S_ISREG(i2->i_mode) && 2301 /* When called by ll_setattr_raw, file is i1. */ 2302 if (LLIF_DATA_MODIFIED & ll_i2info(i1)->lli_flags) 2243 ll_prep_md_op_data(struct md_op_data *op_data, struct inode *i1, struct inode *i2, const char *name, int namelen, int mode, __u32 opc, void *data) argument
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H A D | namei.c | 313 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2) argument 319 LASSERT(i1 != NULL); 322 suppgids[0] = ll_i2suppgid(i1);
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H A D | llite_internal.h | 655 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2); 827 struct inode *i1, struct inode *i2,
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/drivers/isdn/i4l/ |
H A D | isdn_net.c | 2060 isdn_net_swap_usage(int i1, int i2) argument 2062 int u1 = dev->usage[i1] & ISDN_USAGE_EXCLUSIVE; 2066 printk(KERN_DEBUG "n_fi: usage of %d and %d\n", i1, i2); 2068 dev->usage[i1] &= ~ISDN_USAGE_EXCLUSIVE; 2069 dev->usage[i1] |= u2;
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/drivers/scsi/ |
H A D | advansys.c | 404 ASC_SCSIQ_1 i1; member in struct:asc_risc_q
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