Searched refs:readq (Results 1 - 25 of 62) sorted by relevance

123

/drivers/staging/unisys/channels/
H A Dchannel.c54 ((char __iomem *) pChannel + readq(&pChannel->oChannelSpace))
63 nof = readq(&pqhdr->NumOverflows) + 1;
74 psignal = (char __iomem *)pqhdr + readq(&pqhdr->oSignalBase) +
81 writeq(readq(&pqhdr->NumSignalsSent) + 1, &pqhdr->NumSignalsSent);
111 readq(&pChannel->oChannelSpace)) + Queue;
119 writeq(readq(&pqhdr->NumEmptyCnt) + 1, &pqhdr->NumEmptyCnt);
127 psource = (char __iomem *) pqhdr + readq(&pqhdr->oSignalBase) +
134 writeq(readq(&pqhdr->NumSignalsReceived) + 1,
215 readq(&pChannel->oChannelSpace)) + Queue;
/drivers/bluetooth/
H A Dhci_vhci.c51 struct sk_buff_head readq; member in struct:vhci_data
70 skb_queue_purge(&data->readq);
79 skb_queue_purge(&data->readq);
92 skb_queue_tail(&data->readq, skb);
156 skb_queue_tail(&data->readq, skb);
268 skb = skb_dequeue(&data->readq);
272 skb_queue_head(&data->readq, skb);
284 !skb_queue_empty(&data->readq));
306 if (!skb_queue_empty(&data->readq))
328 skb_queue_head_init(&data->readq);
[all...]
/drivers/misc/mic/card/
H A Dmic_virtio.h37 #define ioread64 readq
/drivers/scsi/csiostor/
H A Dcsio_defs.h53 #ifndef readq
54 static inline u64 readq(void __iomem *addr) function
/drivers/staging/unisys/uislib/
H A Duisqueue.c43 j = readq(tgt);
61 j = readq(tgt);
/drivers/net/ethernet/neterion/vxge/
H A Dvxge-config.c38 val64 = readq(&vp_reg->rxmac_vcfg0);
41 val64 = readq(&vp_reg->rxmac_vcfg0);
64 val64 = readq(&vp_reg->prc_cfg6);
74 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
79 val64 = readq(&vp_reg->frm_in_progress_cnt);
127 val64 = readq(reg);
135 val64 = readq(reg);
207 val64 = readq(&vp_reg->rts_access_steer_ctrl);
209 *data0 = readq(&vp_reg->rts_access_steer_data0);
210 *data1 = readq(
[all...]
H A Dvxge-traffic.c86 val64 = readq(&vp_reg->vpath_general_int_status);
236 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
405 val64 = readq(&hldev->common_reg->titan_general_int_status);
622 alarm_status = readq(&vp_reg->vpath_general_int_status);
646 val64 = readq(&vp_reg->xgmac_vp_int_status);
651 val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
707 pic_status = readq(&vp_reg->vpath_ppif_int_status);
712 val64 = readq(&vp_reg->general_errors_reg);
713 mask64 = readq(&vp_reg->general_errors_mask);
760 val64 = readq(
[all...]
/drivers/net/ethernet/neterion/
H A Ds2io.c1022 val64 = readq(&bar0->pci_mode);
1058 val64 = readq(&bar0->pci_mode);
1221 val64 = readq(&bar0->sw_reset);
1228 val64 = readq(&bar0->sw_reset);
1235 val64 = readq(&bar0->adapter_status);
1246 val64 = readq(&bar0->mac_cfg);
1254 val64 = readq(&bar0->mac_int_mask);
1255 val64 = readq(&bar0->mc_int_mask);
1256 val64 = readq(&bar0->xgxs_int_mask);
1274 val64 = readq(
[all...]
/drivers/char/
H A Dhpet.c60 #define read_counter(MC) readq(MC)
127 #ifndef readq
128 static inline unsigned long long readq(void __iomem *addr) function
223 v = (readq(&timer->hpet_config) & Tn_INT_ROUTE_CAP_MASK) >>
429 writeq((readq(&timer->hpet_config) & ~Tn_INT_ENB_CNF_MASK),
438 && readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) {
441 v = readq(&timer->hpet_config);
523 v = readq(&timer->hpet_config);
609 v = readq(&timer->hpet_config);
625 readq(
[all...]
/drivers/net/ethernet/intel/i40evf/
H A Di40e_osdep.h36 /* get readq/writeq support for 32 bit kernels, use the low-first version */
49 #define rd64(a, reg) readq((a)->hw_addr + (reg))
/drivers/net/ethernet/cisco/enic/
H A Dvnic_dev.h30 #ifndef readq
31 static inline u64 readq(void __iomem *reg) function
/drivers/ntb/
H A Dntb_hw.h64 #ifndef readq
65 static inline u64 readq(void __iomem *addr) function
/drivers/scsi/fnic/
H A Dvnic_dev.h69 #ifndef readq
70 static inline u64 readq(void __iomem *reg) function
H A Dvnic_dev.c273 err = dev_cmd_err[(int)readq(&devcmd->args[0])];
281 *a0 = readq(&devcmd->args[0]);
282 *a1 = readq(&devcmd->args[1]);
/drivers/char/agp/
H A Dparisc-agp.c98 readq(info->ioc_regs+IOC_PCOM); /* flush */
252 io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG);
268 iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1;
274 io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE));
H A Dhp-agp.c89 hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG);
105 hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1;
111 hp->io_pdir = phys_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE));
175 hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0;
273 readq(hp->ioc_regs+HP_ZX1_IBASE);
287 readq(hp->ioc_regs+HP_ZX1_PCOM);
/drivers/infiniband/hw/qib/
H A Dqib_7220.h134 return readq(&dd->kregbase[regno]);
/drivers/net/ethernet/intel/i40e/
H A Di40e_osdep.h37 /* get readq/writeq support for 32 bit kernels, use the low-first version */
50 #define rd64(a, reg) readq((a)->hw_addr + (reg))
/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dadapter.h413 #ifndef readq
414 static inline u64 readq(const volatile void __iomem *addr) function
435 return readq(adapter->regs + reg_addr);
/drivers/edac/
H A Di3200_edac.c200 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
202 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
213 info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
215 info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
/drivers/idle/
H A Di7300_idle.c129 sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
163 chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
291 chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
301 chan_sts = readq(ioat_chanbase + IOAT1_CHANSTS_OFFSET) &
/drivers/input/misc/
H A Dsgi_btns.c45 status = readq(&mace->perif.audio.control);
/drivers/staging/unisys/common-spar/include/channels/
H A Dchannel.h367 if (readq(&((CHANNEL_HEADER __iomem *)
371 readq(&((CHANNEL_HEADER __iomem *)
390 if (readq(&((CHANNEL_HEADER __iomem *) (pChannel))->Signature)
394 readq(&((CHANNEL_HEADER __iomem *)
/drivers/infiniband/hw/amso1100/
H A Dc2.h404 #ifndef readq
405 static inline u64 readq(const void __iomem * addr) function
/drivers/base/regmap/
H A Dregmap-mmio.c179 *(u64 *)val = readq(ctx->regs + offset);

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