Searched refs:val (Results 1 - 25 of 3672) sorted by relevance

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/drivers/net/wireless/brcm80211/brcmsmac/
H A Dtypes.h133 #define CONF_HAS(config, val) ((config) & (1 << (val)))
138 #define CONF_IS(config, val) ((config) == (1 << (val)))
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val))))
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
141 #define CONF_LT(config, val) ((config) & ((1 << (val))
[all...]
/drivers/net/ethernet/neterion/vxge/
H A Dvxge-reg.h23 * vxge_vBIT(val, loc, sz) - set bits at offset
25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4)
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4)
56 #define VXGE_EPROM_IMG_FIX(val) (u3
[all...]
/drivers/media/tuners/
H A Dtda18271-maps.c31 u8 val; member in struct:tda18271_map
202 { .rfmax = 62000, .val = 0x00 },
203 { .rfmax = 84000, .val = 0x01 },
204 { .rfmax = 100000, .val = 0x02 },
205 { .rfmax = 140000, .val = 0x03 },
206 { .rfmax = 170000, .val = 0x04 },
207 { .rfmax = 180000, .val = 0x05 },
208 { .rfmax = 865000, .val = 0x06 },
209 { .rfmax = 0, .val = 0x00 }, /* end */
213 { .rfmax = 61100, .val
936 int val, i = 0; local
1118 tda18271_lookup_map(struct dvb_frontend *fe, enum tda18271_map_type map_type, u32 *freq, u8 *val) argument
[all...]
/drivers/gpu/drm/msm/adreno/
H A Da3xx.xml.h571 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) argument
573 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
577 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) argument
579 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
585 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) argument
587 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
593 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) argument
595 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
601 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) argument
603 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIF
609 A3XX_GRAS_CL_VPORT_YSCALE(float val) argument
617 A3XX_GRAS_CL_VPORT_ZOFFSET(float val) argument
625 A3XX_GRAS_CL_VPORT_ZSCALE(float val) argument
633 A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) argument
639 A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) argument
647 A3XX_GRAS_SU_POINT_SIZE(float val) argument
655 A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) argument
663 A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) argument
674 A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) argument
683 A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) argument
689 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) argument
695 A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) argument
704 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) argument
710 A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) argument
719 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) argument
725 A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) argument
734 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) argument
740 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) argument
749 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) argument
755 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) argument
764 A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) argument
775 A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) argument
788 A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) argument
797 A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) argument
803 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) argument
811 A3XX_RB_ALPHA_REF_UINT(uint32_t val) argument
817 A3XX_RB_ALPHA_REF_FLOAT(float val) argument
830 A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) argument
836 A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) argument
842 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) argument
850 A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) argument
856 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) argument
862 A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) argument
868 A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) argument
876 A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) argument
884 A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) argument
890 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) argument
896 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) argument
902 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) argument
908 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) argument
914 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) argument
923 A3XX_RB_BLEND_RED_UINT(uint32_t val) argument
929 A3XX_RB_BLEND_RED_FLOAT(float val) argument
937 A3XX_RB_BLEND_GREEN_UINT(uint32_t val) argument
943 A3XX_RB_BLEND_GREEN_FLOAT(float val) argument
951 A3XX_RB_BLEND_BLUE_UINT(uint32_t val) argument
957 A3XX_RB_BLEND_BLUE_FLOAT(float val) argument
965 A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) argument
971 A3XX_RB_BLEND_ALPHA_FLOAT(float val) argument
987 A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) argument
994 A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) argument
1000 A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) argument
1006 A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) argument
1014 A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) argument
1022 A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) argument
1030 A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) argument
1036 A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) argument
1042 A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) argument
1048 A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) argument
1054 A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) argument
1060 A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) argument
1072 A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) argument
1084 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) argument
1090 A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) argument
1098 A3XX_RB_DEPTH_PITCH(uint32_t val) argument
1109 A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) argument
1115 A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) argument
1121 A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) argument
1127 A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) argument
1133 A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) argument
1139 A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) argument
1145 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) argument
1151 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) argument
1165 A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) argument
1171 A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) argument
1177 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) argument
1185 A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) argument
1191 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) argument
1197 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) argument
1208 A3XX_RB_WINDOW_OFFSET_X(uint32_t val) argument
1214 A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) argument
1236 A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) argument
1242 A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) argument
1252 A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) argument
1258 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) argument
1264 A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) argument
1276 A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) argument
1293 A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) argument
1304 A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) argument
1312 A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) argument
1320 A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument
1326 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) argument
1332 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument
1340 A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) argument
1346 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) argument
1352 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) argument
1360 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) argument
1366 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) argument
1374 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) argument
1380 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) argument
1388 A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) argument
1394 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) argument
1400 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) argument
1406 A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) argument
1436 A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) argument
1442 A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) argument
1448 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) argument
1454 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) argument
1462 A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) argument
1468 A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) argument
1474 A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) argument
1492 A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) argument
1498 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) argument
1505 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) argument
1511 A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) argument
1523 A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) argument
1530 A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) argument
1536 A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) argument
1542 A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) argument
1548 A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) argument
1558 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) argument
1564 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) argument
1572 A3XX_VPC_ATTR_TOTALATTR(uint32_t val) argument
1579 A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) argument
1585 A3XX_VPC_ATTR_LMSIZE(uint32_t val) argument
1593 A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) argument
1599 A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) argument
1620 A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) argument
1627 A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) argument
1633 A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) argument
1641 A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument
1647 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) argument
1654 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument
1660 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument
1666 A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) argument
1672 A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) argument
1681 A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) argument
1689 A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) argument
1695 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) argument
1701 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) argument
1709 A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) argument
1715 A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) argument
1721 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) argument
1731 A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) argument
1737 A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) argument
1743 A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) argument
1749 A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) argument
1759 A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) argument
1765 A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) argument
1771 A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) argument
1777 A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) argument
1785 A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument
1791 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument
1807 A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) argument
1815 A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) argument
1821 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) argument
1828 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) argument
1834 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) argument
1840 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) argument
1846 A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) argument
1855 A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) argument
1863 A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) argument
1869 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) argument
1875 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) argument
1881 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) argument
1889 A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) argument
1895 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) argument
1916 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) argument
1926 A3XX_SP_FS_MRT_REG_REGID(uint32_t val) argument
1937 A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) argument
1945 A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) argument
1953 A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) argument
1959 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) argument
1965 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) argument
1975 A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) argument
1981 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) argument
1987 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) argument
2071 A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) argument
2077 A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) argument
2089 A3XX_VSC_PIPE_CONFIG_X(uint32_t val) argument
2095 A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) argument
2101 A3XX_VSC_PIPE_CONFIG_W(uint32_t val) argument
2107 A3XX_VSC_PIPE_CONFIG_H(uint32_t val) argument
2160 A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) argument
2166 A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) argument
2214 A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) argument
2222 A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) argument
2228 A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) argument
2275 A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) argument
2281 A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) argument
2287 A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) argument
2293 A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) argument
2302 A3XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val) argument
2313 A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) argument
2319 A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) argument
2325 A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) argument
2331 A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) argument
2337 A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) argument
2343 A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) argument
2352 A3XX_TEX_SAMP_1_MAX_LOD(float val) argument
2358 A3XX_TEX_SAMP_1_MIN_LOD(float val) argument
2368 A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) argument
2374 A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) argument
2380 A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) argument
2386 A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) argument
2392 A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) argument
2398 A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) argument
2405 A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) argument
2413 A3XX_TEX_CONST_1_HEIGHT(uint32_t val) argument
2419 A3XX_TEX_CONST_1_WIDTH(uint32_t val) argument
2425 A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) argument
2433 A3XX_TEX_CONST_2_INDX(uint32_t val) argument
2439 A3XX_TEX_CONST_2_PITCH(uint32_t val) argument
2445 A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) argument
[all...]
H A Dadreno_pm4.xml.h208 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) argument
210 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
214 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) argument
216 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
220 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) argument
222 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
226 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) argument
228 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
234 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) argument
236 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIF
240 CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) argument
248 CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) argument
256 CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) argument
262 CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) argument
268 CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) argument
274 CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) argument
283 CP_DRAW_INDX_1_NUM_INDICES(uint32_t val) argument
291 CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) argument
299 CP_DRAW_INDX_2_INDX_BASE(uint32_t val) argument
307 CP_DRAW_INDX_2_INDX_SIZE(uint32_t val) argument
315 CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) argument
323 CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) argument
329 CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) argument
335 CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) argument
341 CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) argument
350 CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val) argument
358 CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) argument
366 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) argument
372 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) argument
378 CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) argument
384 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val) argument
393 CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val) argument
403 CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) argument
411 CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val) argument
419 CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val) argument
427 CP_SET_DRAW_STATE_0_COUNT(uint32_t val) argument
437 CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val) argument
445 CP_SET_DRAW_STATE_1_ADDR(uint32_t val) argument
455 CP_SET_BIN_1_X1(uint32_t val) argument
461 CP_SET_BIN_1_Y1(uint32_t val) argument
469 CP_SET_BIN_2_X2(uint32_t val) argument
475 CP_SET_BIN_2_Y2(uint32_t val) argument
483 CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) argument
491 CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) argument
[all...]
H A Da2xx.xml.h262 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
264 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
268 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
270 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
274 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
276 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
280 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
282 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
286 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
288 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIF
292 A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
298 A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
304 A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
310 A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
316 A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
322 A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) argument
384 A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) argument
411 A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) argument
421 A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) argument
430 A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) argument
443 A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) argument
449 A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) argument
541 A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) argument
552 A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) argument
562 A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) argument
569 A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) argument
575 A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) argument
594 A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) argument
600 A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) argument
607 A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) argument
613 A2XX_RB_COLOR_INFO_SWAP(uint32_t val) argument
619 A2XX_RB_COLOR_INFO_BASE(uint32_t val) argument
627 A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) argument
633 A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) argument
646 A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) argument
652 A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) argument
661 A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) argument
667 A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) argument
675 A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) argument
681 A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) argument
691 A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) argument
697 A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) argument
706 A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) argument
712 A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) argument
746 A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) argument
752 A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) argument
758 A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) argument
766 A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) argument
772 A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) argument
778 A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) argument
788 A2XX_PA_CL_VPORT_XSCALE(float val) argument
796 A2XX_PA_CL_VPORT_XOFFSET(float val) argument
804 A2XX_PA_CL_VPORT_YSCALE(float val) argument
812 A2XX_PA_CL_VPORT_YOFFSET(float val) argument
820 A2XX_PA_CL_VPORT_ZSCALE(float val) argument
828 A2XX_PA_CL_VPORT_ZOFFSET(float val) argument
836 A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) argument
842 A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) argument
852 A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) argument
858 A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) argument
864 A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) argument
875 A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) argument
881 A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) argument
904 A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) argument
910 A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) argument
916 A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) argument
922 A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) argument
931 A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val) argument
945 A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) argument
952 A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) argument
958 A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) argument
964 A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) argument
970 A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) argument
976 A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) argument
982 A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) argument
988 A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) argument
994 A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) argument
1002 A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) argument
1008 A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) argument
1014 A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) argument
1020 A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) argument
1026 A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) argument
1032 A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) argument
1042 A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) argument
1053 A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) argument
1059 A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) argument
1065 A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) argument
1072 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) argument
1078 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) argument
1084 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) argument
1090 A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) argument
1098 A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) argument
1104 A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) argument
1110 A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) argument
1120 A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) argument
1136 A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) argument
1142 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) argument
1148 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) argument
1184 A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) argument
1190 A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) argument
1196 A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) argument
1204 A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) argument
1216 A2XX_CLEAR_COLOR_RED(uint32_t val) argument
1222 A2XX_CLEAR_COLOR_GREEN(uint32_t val) argument
1228 A2XX_CLEAR_COLOR_BLUE(uint32_t val) argument
1234 A2XX_CLEAR_COLOR_ALPHA(uint32_t val) argument
1244 A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) argument
1250 A2XX_PA_SU_POINT_SIZE_WIDTH(float val) argument
1258 A2XX_PA_SU_POINT_MINMAX_MIN(float val) argument
1264 A2XX_PA_SU_POINT_MINMAX_MAX(float val) argument
1272 A2XX_PA_SU_LINE_CNTL_WIDTH(float val) argument
1280 A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) argument
1286 A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) argument
1292 A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) argument
1298 A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) argument
1310 A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) argument
1323 A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) argument
1329 A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) argument
1335 A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) argument
1343 A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) argument
1351 A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) argument
1359 A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) argument
1367 A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) argument
1375 A2XX_SQ_VS_CONST_BASE(uint32_t val) argument
1381 A2XX_SQ_VS_CONST_SIZE(uint32_t val) argument
1389 A2XX_SQ_PS_CONST_BASE(uint32_t val) argument
1395 A2XX_SQ_PS_CONST_SIZE(uint32_t val) argument
1413 A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) argument
1420 A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) argument
1430 A2XX_RB_COPY_DEST_PITCH(uint32_t val) argument
1438 A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) argument
1445 A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) argument
1451 A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) argument
1457 A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) argument
1463 A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) argument
1475 A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) argument
1481 A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) argument
1519 A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) argument
1525 A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) argument
1531 A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) argument
1537 A2XX_SQ_TEX_0_PITCH(uint32_t val) argument
1547 A2XX_SQ_TEX_2_WIDTH(uint32_t val) argument
1553 A2XX_SQ_TEX_2_HEIGHT(uint32_t val) argument
1561 A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) argument
1567 A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) argument
1573 A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) argument
1579 A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) argument
1585 A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) argument
1591 A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) argument
[all...]
H A Dadreno_common.xml.h148 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) argument
150 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
154 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) argument
156 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
160 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) argument
162 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
171 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) argument
173 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
177 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) argument
179 return ((val >>
195 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) argument
201 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) argument
207 AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) argument
215 AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) argument
221 AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) argument
229 AXXX_CP_CSQ_AVAIL_RING(uint32_t val) argument
235 AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) argument
241 AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) argument
249 AXXX_CP_STQ_AVAIL_ST(uint32_t val) argument
257 AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) argument
265 AXXX_SCRATCH_UMSK_UMSK(uint32_t val) argument
271 AXXX_SCRATCH_UMSK_SWAP(uint32_t val) argument
315 AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) argument
321 AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) argument
329 AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) argument
335 AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) argument
343 AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) argument
349 AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) argument
[all...]
/drivers/media/pci/cx18/
H A Dcx18-io.c27 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) argument
30 u16 val2 = val | (val << 8);
35 cx18_writeb(cx, (u8) val, dst);
55 cx18_writeb(cx, (u8) val, dst);
58 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) argument
60 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
61 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
65 cx18_sw1_irq_disable(struct cx18 *cx, u32 val) argument
71 cx18_sw2_irq_enable(struct cx18 *cx, u32 val) argument
78 cx18_sw2_irq_disable(struct cx18 *cx, u32 val) argument
84 cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) argument
93 u32 val; local
[all...]
H A Dcx18-io.h44 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) argument
46 __raw_writel(val, addr);
49 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) argument
53 cx18_raw_writel_noretry(cx, val, addr);
54 if (val == cx18_raw_readl(cx, addr))
66 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) argument
68 writel(val, addr);
71 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) argument
75 cx18_writel_noretry(cx, val, addr);
76 if (val
82 cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, u32 eval, u32 mask) argument
104 cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) argument
109 cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) argument
125 cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) argument
130 cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) argument
151 cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) argument
156 cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) argument
161 cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, u32 eval, u32 mask) argument
174 cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) argument
[all...]
/drivers/gpu/drm/msm/dsi/
H A Dmmss_cc.xml.h70 static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val) argument
72 return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
76 static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val) argument
78 return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
84 static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val) argument
86 return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
90 static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val) argument
92 return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
98 static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val) argument
100 return ((val) << MMSS_CC_CLK_NS_SRC__SHIF
104 MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val) argument
110 MMSS_CC_CLK_NS_VAL(uint32_t val) argument
[all...]
/drivers/net/ethernet/chelsio/cxgb/
H A Dmy3126.c38 u32 val; local
46 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
47 val16 = (u16) val;
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
66 act_count += val;
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
70 cphy->elmer_gpo = val;
72 if ( (val & (1 << 8)) || (val & (1 << 19)) ||
75 val |
112 u32 val; local
188 u32 val; local
[all...]
/drivers/net/wimax/i2400m/
H A Dsysfs.c48 unsigned val; local
51 if (sscanf(buf, "%u\n", &val) != 1)
53 if (val != 0 && (val < 100 || val > 300000 || val % 100 != 0)) {
56 val);
59 result = i2400m_set_idle_timeout(i2400m, val);
/drivers/net/wireless/ti/wl18xx/
H A Dio.c27 int wl18xx_top_reg_write(struct wl1271 *wl, int addr, u16 val) argument
40 tmp = (tmp & 0xffff0000) | val;
47 tmp = (tmp & 0xffff) | (val << 16);
57 u32 val = 0; local
65 ret = wlcore_read32(wl, addr, &val);
67 *out = val & 0xffff;
69 ret = wlcore_read32(wl, addr - 2, &val);
71 *out = (val & 0xffff0000) >> 16;
/drivers/input/serio/
H A Di8042-ppcio.h35 static inline void i8042_write_data(int val) argument
37 writeb(val, kb_data);
40 static inline void i8042_write_command(int val) argument
42 writeb(val, kb_cs);
/drivers/clk/qcom/
H A Dclk-regmap.c33 unsigned int val; local
36 ret = regmap_read(rclk->regmap, rclk->enable_reg, &val);
41 return (val & rclk->enable_mask) == 0;
43 return (val & rclk->enable_mask) != 0;
59 unsigned int val; local
62 val = 0;
64 val = rclk->enable_mask;
67 rclk->enable_mask, val);
83 unsigned int val; local
86 val
[all...]
/drivers/gpu/drm/i915/
H A Dintel_sideband.c43 u32 port, u32 opcode, u32 addr, u32 *val)
62 I915_WRITE(VLV_IOSF_DATA, *val);
72 *val = I915_READ(VLV_IOSF_DATA);
80 u32 val = 0; local
86 SB_CRRDDA_NP, addr, &val);
89 return val;
92 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) argument
98 SB_CRWRDA_NP, addr, &val);
104 u32 val = 0; local
107 SB_CRRDDA_NP, reg, &val);
42 vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, u32 port, u32 opcode, u32 addr, u32 *val) argument
112 vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
120 u32 val = 0; local
134 u32 val = 0; local
140 vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
148 u32 val = 0; local
154 vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
162 u32 val = 0; local
168 vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
176 u32 val = 0; local
182 vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
190 u32 val = 0; local
205 vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) argument
272 u32 val = 0; local
278 vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) argument
[all...]
/drivers/usb/phy/
H A Dphy-tegra-usb.c209 unsigned long val; local
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
220 writel(val, base + TEGRA_USB_PORTSC1);
227 unsigned long val; local
259 unsigned long val, flags; local
290 unsigned long val, flags; local
329 unsigned long val; local
351 unsigned long val; local
374 unsigned long val; local
523 unsigned long val; local
558 unsigned long val; local
568 unsigned long val; local
579 unsigned long val; local
599 unsigned long val; local
611 unsigned long val; local
[all...]
/drivers/soc/tegra/fuse/
H A Dspeedo-tegra20.c68 u32 val; local
81 val = 0;
85 val = (val << 1) | (reg & 0x1);
87 val = val * SPEEDO_MULT;
88 pr_debug("Tegra CPU speedo value %u\n", val);
91 if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
96 val = 0;
100 val
[all...]
/drivers/watchdog/
H A Dsp5100_tco.c78 u32 val; local
82 val = readl(SP5100_WDT_CONTROL(tcobase));
83 val |= SP5100_WDT_START_STOP_BIT;
84 writel(val, SP5100_WDT_CONTROL(tcobase));
90 u32 val; local
94 val = readl(SP5100_WDT_CONTROL(tcobase));
95 val &= ~SP5100_WDT_START_STOP_BIT;
96 writel(val, SP5100_WDT_CONTROL(tcobase));
102 u32 val; local
106 val
130 int val; local
320 u32 val; local
[all...]
/drivers/phy/
H A Dphy-xgene.c566 u32 val; local
576 val = readl(csr_base + indirect_cmd_reg);
577 } while (!(val & CFG_IND_CMD_DONE_MASK) &&
579 if (!(val & CFG_IND_CMD_DONE_MASK))
588 u32 val; local
596 val = readl(csr_base + indirect_cmd_reg);
597 } while (!(val & CFG_IND_CMD_DONE_MASK) &&
600 if (!(val & CFG_IND_CMD_DONE_MASK))
609 u32 val; local
618 SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
639 u32 val; local
652 u32 val; local
662 u32 val; local
672 u32 val; local
698 u32 val; local
708 u32 val; local
719 u32 val; local
773 u32 val; local
927 u32 val; local
952 u32 val; local
1151 u32 val; local
1249 u32 val; local
1267 u32 val; local
1359 u32 val; member in struct:__anon4807
1446 u32 val; local
[all...]
/drivers/net/wireless/ath/ath5k/
H A Deeprom.c43 u16 val; local
50 val = (5 * bin) + 4800;
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
56 val = bin + 2300;
58 val = bin + 2400;
61 return val;
76 u16 val; local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
97 if (val) {
98 eep_max = (val
119 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); local
194 u16 val; local
254 u16 val; local
517 u16 val; local
553 u16 val; local
799 u16 val; local
1024 u16 val; local
1287 u16 val; local
1476 u16 val; local
1606 u16 val; local
1709 u16 val; local
[all...]
/drivers/gpu/host1x/hw/
H A Ddebug_hw.c41 static unsigned int show_channel_command(struct output *o, u32 val) argument
46 switch (val >> 28) {
48 mask = val & 0x3f;
51 val >> 6 & 0x3ff,
52 val >> 16 & 0xfff, mask);
56 val >> 6 & 0x3ff);
62 val >> 16 & 0xfff);
63 return val & 0xffff;
67 val >> 16 & 0xfff);
68 return val
128 u32 val = *(map_addr + offset / 4 + i); local
185 u32 val, base, baseval; local
236 u32 val, rd_ptr, wr_ptr, start, end; local
[all...]
/drivers/hwmon/
H A Dhwmon-vid.c78 * val is the 4-bit or more VID code.
82 int vid_from_reg(int val, u8 vrm) argument
90 val &= 0x3f;
91 if ((val & 0x1f) == 0x1f)
93 if ((val & 0x1f) <= 0x09 || val == 0x0a)
94 vid = 1087500 - (val & 0x1f) * 25000;
96 vid = 1862500 - (val & 0x1f) * 25000;
97 if (val & 0x20)
103 val
[all...]
/drivers/mfd/
H A Dpcf50633-gpio.c38 int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) argument
44 return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
50 u8 reg, val; local
53 val = pcf50633_reg_read(pcf, reg) & 0x07;
55 return val;
61 u8 val, reg; local
64 val = !!invert << 3;
66 return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
72 u8 reg, val; local
75 val
84 u8 reg, val, mask; local
[all...]
/drivers/media/pci/bt8xx/
H A Dbttv-audio-hook.c78 unsigned int val, con; local
83 val = gpio_read();
96 if (con != (val & 0x300)) {
102 switch (val & 0x70) {
145 int val = 0; local
149 val = 0x02;
151 val = 0x01;
152 if (val) {
153 gpio_bits(0x03,val);
167 int val local
188 int val = 0; local
237 unsigned long val = 0; local
270 unsigned int val = 0; local
301 unsigned int val = 0xffff; local
331 unsigned long val = 0; local
[all...]

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