Searched refs:wptr (Results 1 - 25 of 38) sorted by relevance

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/drivers/media/usb/pvrusb2/
H A Dpvrusb2-debugifc.c69 const char *wptr; local
74 wptr = NULL;
82 wptr = buf;
87 *wstrPtr = wptr;
198 const char *wptr; local
202 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
205 if (!wptr) return 0;
207 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr);
208 if (debugifc_match_keyword(wptr,wlen,"reset")) {
209 scnt = debugifc_isolate_word(buf,count,&wptr,
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/drivers/gpu/drm/radeon/
H A Dvce_v1_0.c80 WREG32(VCE_RB_WPTR, ring->wptr);
82 WREG32(VCE_RB_WPTR2, ring->wptr);
101 WREG32(VCE_RB_RPTR, ring->wptr);
102 WREG32(VCE_RB_WPTR, ring->wptr);
108 WREG32(VCE_RB_RPTR2, ring->wptr);
109 WREG32(VCE_RB_WPTR2, ring->wptr);
H A Dradeon_ring.c38 * GPU is currently reading, and a wptr (write pointer)
42 * wptr. The GPU then starts fetching commands and executes
84 ring->ring_free_dw -= ring->wptr;
125 ring->wptr_old = ring->wptr;
161 * Update the wptr (write pointer) to tell the GPU to
173 while (ring->wptr & ring->align_mask) {
203 * radeon_ring_undo - reset the wptr
207 * Reset the driver's copy of the wptr (all asics).
211 ring->wptr = ring->wptr_old;
215 * radeon_ring_unlock_undo - reset the wptr an
468 uint32_t rptr, wptr, rptr_next; local
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H A Dni_dma.c78 * Get the current wptr from the hardware (cayman+).
99 * Write the wptr back to the hardware (cayman+).
111 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
128 u32 next_rptr = ring->wptr + 4;
141 while ((ring->wptr & 7) != 5)
242 ring->wptr = 0;
243 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
H A Devergreen_dma.c73 u32 next_rptr = ring->wptr + 4;
86 while ((ring->wptr & 7) != 5)
H A Dr600_dma.c70 * Get the current wptr from the hardware (r6xx+).
84 * Write the wptr back to the hardware (r6xx+).
89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
167 ring->wptr = 0;
168 WREG32(DMA_RB_WPTR, ring->wptr << 2);
405 u32 next_rptr = ring->wptr + 4;
418 while ((ring->wptr & 7) != 5)
H A Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
369 ring->wptr = RREG32(UVD_RBC_RB_RPTR);
370 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
H A Dr600.c2553 u32 wptr; local
2555 wptr = RREG32(R600_CP_RB_WPTR);
2557 return wptr;
2563 WREG32(R600_CP_RB_WPTR, ring->wptr);
2667 ring->wptr = 0;
2668 WREG32(CP_RB_WPTR, ring->wptr);
3262 next_rptr = ring->wptr + 3 + 4;
3268 next_rptr = ring->wptr + 5 + 4;
3346 * increments the rptr. When the rptr catches up with the wptr, all the
3495 /* set rptr, wptr t
3920 u32 wptr, tmp; local
3975 u32 wptr; local
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H A Dcik_sdma.c88 * Get the current wptr from the hardware (CIK+).
109 * Write the wptr back to the hardware (CIK+).
121 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
140 u32 next_rptr = ring->wptr + 5;
152 while ((ring->wptr & 7) != 4)
371 ring->wptr = 0;
372 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
H A Dni.c1384 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1444 u32 wptr; local
1447 wptr = RREG32(CP_RB0_WPTR);
1449 wptr = RREG32(CP_RB1_WPTR);
1451 wptr = RREG32(CP_RB2_WPTR);
1453 return wptr;
1460 WREG32(CP_RB0_WPTR, ring->wptr);
1463 WREG32(CP_RB1_WPTR, ring->wptr);
1466 WREG32(CP_RB2_WPTR, ring->wptr);
1666 ring->wptr
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/drivers/net/ppp/
H A Dbsd_comp.c580 unsigned char *wptr; local
586 if (wptr) \
588 *wptr++ = (unsigned char) (v); \
591 wptr = NULL; \
630 wptr = obuf;
639 if (wptr)
641 *wptr++ = PPP_ADDRESS(rptr);
642 *wptr++ = PPP_CONTROL(rptr);
643 *wptr++ = 0;
644 *wptr
843 unsigned char *wptr; local
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H A Dppp_deflate.c193 unsigned char *wptr; local
207 wptr = obuf;
212 wptr[0] = PPP_ADDRESS(rptr);
213 wptr[1] = PPP_CONTROL(rptr);
214 put_unaligned_be16(PPP_COMP, wptr + 2);
215 wptr += PPP_HDRLEN;
216 put_unaligned_be16(state->seqno, wptr);
217 wptr += DEFLATE_OVHD;
219 state->strm.next_out = wptr;
/drivers/video/fbdev/
H A Dmaxinefb.c67 unsigned char *wptr; local
69 wptr = regs + 0xa0000 + (regno << 4);
71 *((volatile unsigned short *) (wptr)) = val;
/drivers/net/ethernet/tehuti/
H A Dtehuti.c172 f->wptr = 0;
1116 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1124 f->m.wptr += sizeof(struct rxf_desc);
1125 delta = f->m.wptr - f->m.memsz;
1127 f->m.wptr = delta;
1135 /*TBD: to do - delayed rxf wptr like in txd */
1136 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1173 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1181 f->m.wptr += sizeof(struct rxf_desc);
1182 delta = f->m.wptr
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H A Dtehuti.h146 u32 rptr, wptr; /* cached values of RPTR and WPTR registers, member in struct:fifo
202 struct tx_map *wptr; /* points to the next element to write */ member in struct:txdb
/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.c108 adreno_gpu->memptrs->wptr = 0;
191 uint32_t wptr = get_wptr(gpu->rb); local
196 gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
202 uint32_t wptr = get_wptr(gpu->rb); local
205 if (spin_until(adreno_gpu->memptrs->rptr == wptr))
225 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
226 seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
261 printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
282 uint32_t wptr = get_wptr(gpu->rb); local
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H A Dadreno_gpu.h55 volatile uint32_t wptr; member in struct:adreno_rbmemptrs
73 /* ringbuffer rptr/wptr: */
/drivers/staging/media/lirc/
H A Dlirc_parallel.c85 static unsigned int wptr; variable
210 nwptr = (wptr + 1) & (RBUF_SIZE - 1);
217 rbuf[wptr] = signal;
218 wptr = nwptr;
338 if (rptr != wptr) {
457 if (rptr != wptr)
524 wptr = 0;
/drivers/tty/serial/
H A Dmen_z135_uart.c294 u32 wptr; local
316 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
317 txc = (wptr >> 16) & 0x3ff;
318 wptr &= 0x3ff;
333 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
334 n = 4 - BYTES_TO_ALIGN(wptr);
445 u32 wptr; local
448 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
449 txc = (wptr >> 16) & 0x3ff;
/drivers/infiniband/hw/cxgb3/
H A Dcxio_hal.c435 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
608 PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
609 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
613 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
617 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
620 rdev_p->ctrl_qp.wptr,
629 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
671 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
674 /* wptr in the WRID[31:0] */
675 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
706 u32 wptr; local
767 u32 wptr; local
1120 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2); local
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H A Dcxio_wr.h46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr))
47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \
48 ((rptr)!=(wptr)) )
50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr)))
51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr))
697 u32 wptr; /* id member in struct:t3_wq
718 u32 wptr; member in struct:t3_cq
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H A Diwch_qp.c175 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
177 Q_GENBIT(wq->wptr + 1, wq->size_log2),
384 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
443 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
452 qhp->wq.wptr += wr_cnt;
494 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
508 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
514 ++(qhp->wq.wptr);
561 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
598 Q_GENBIT(qhp->wq.wptr, qh
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/drivers/tty/
H A Dmoxa.c275 u16 rptr, wptr, mask, len; local
279 wptr = readw(ofsAddr + RXwptr);
281 len = (wptr - rptr) & mask;
1997 u16 rptr, wptr, mask; local
2000 wptr = readw(ofsAddr + TXwptr);
2002 return (wptr - rptr) & mask;
2008 u16 rptr, wptr, mask; local
2011 wptr = readw(ofsAddr + TXwptr);
2013 return mask - ((wptr - rptr) & mask);
2019 u16 rptr, wptr, mas local
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/drivers/scsi/qla2xxx/
H A Dqla_sup.c550 uint16_t cnt, chksum, *wptr; local
611 wptr = (uint16_t *)req->ring;
614 chksum += le16_to_cpu(*wptr++);
668 uint16_t *wptr; local
689 wptr = (uint16_t *)req->ring;
694 if (*wptr == __constant_cpu_to_le16(0xffff))
706 chksum += le16_to_cpu(*wptr++);
884 uint16_t *wptr; local
891 wptr = (uint16_t *)req->ring;
895 if (*wptr
983 uint32_t *wptr; local
1035 uint16_t *wptr; local
1325 uint16_t *wptr; local
1365 uint16_t *wptr; local
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/drivers/scsi/
H A Dqla1280.c608 uint16_t *wptr; local
620 wptr = (uint16_t *)&ha->nvram;
624 *wptr = qla1280_get_nvram_word(ha, cnt);
625 chksum += *wptr & 0xff;
626 chksum += (*wptr >> 8) & 0xff;
627 wptr++;
636 *wptr = qla1280_get_nvram_word(ha, cnt);
637 chksum += *wptr & 0xff;
638 chksum += (*wptr >> 8) & 0xff;
639 wptr
3421 uint16_t *wptr; local
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