Searched refs:port (Results 1 - 25 of 1295) sorted by path

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/drivers/acpi/
H A Dosl.c892 acpi_status acpi_os_read_port(acpi_io_address port, u32 * value, u32 width) argument
901 *(u8 *) value = inb(port);
903 *(u16 *) value = inw(port);
905 *(u32 *) value = inl(port);
915 acpi_status acpi_os_write_port(acpi_io_address port, u32 value, u32 width) argument
918 outb(value, port);
920 outw(value, port);
922 outl(value, port);
/drivers/ata/
H A Dlibahci_platform.c311 u32 port; local
316 if (of_property_read_u32(child, "reg", &port)) {
321 if (port >= hpriv->nports) {
322 dev_warn(dev, "invalid port number %d\n", port);
326 mask_port_map |= BIT(port);
328 hpriv->phys[port] = devm_of_phy_get(dev, child, NULL);
329 if (IS_ERR(hpriv->phys[port])) {
330 rc = PTR_ERR(hpriv->phys[port]);
340 dev_warn(dev, "No port enable
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H A Dlibata-core.c115 int port; member in struct:ata_force_ent
182 * @ap: ATA port containing links to iterate
318 * @ap: ATA port of interest
321 * The last entry which has matching port number is used, so it
336 if (fe->port != -1 && fe->port != ap->print_id)
353 * and whine about it. When only the port part is specified
376 if (fe->port != -1 && fe->port != link->ap->print_id)
417 /* allow n.15/16 for devices attached to host port */
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H A Dlibata-sff.c75 * @ap: port where the device is
92 * @ap: port where the device is
113 * @ap: port where the device is
115 * Determine if the port is currently busy. Uses altstatus
202 * @ap: port containing status register to be polled
232 "port is slow to respond, please be patient (Status 0x%x)\n",
247 "port failed to respond (%lu secs, Status 0x%x)\n",
285 * @ap: port where the device is
370 * ata_sff_irq_on - Enable interrupts on a port.
506 * @ap: port t
2258 ata_resources_present(struct pci_dev *pdev, int port) argument
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H A Dpata_atp867x.c86 #define ATP867X_IO_PORTBASE(ap, port) (0x00 + ATP867X_IOBASE(ap) + \
87 (port) * ATP867X_IO_CHANNEL_OFFSET)
88 #define ATP867X_IO_DMABASE(ap, port) (0x40 + \
89 ATP867X_IO_PORTBASE((ap), (port)))
91 #define ATP867X_IO_STATUS(ap, port) (0x07 + \
92 ATP867X_IO_PORTBASE((ap), (port)))
93 #define ATP867X_IO_ALTSTATUS(ap, port) (0x0E + \
94 ATP867X_IO_PORTBASE((ap), (port)))
99 #define ATP867X_IO_MSTRPIOSPD(ap, port) (0x08 + \
100 ATP867X_IO_DMABASE((ap), (port)))
300 atp867x_check_ports(struct ata_port *ap, int port) argument
353 int port = ap->port_no; local
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H A Dpata_ep93xx.c661 drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
669 drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
H A Dpata_icside.c58 } port[2]; member in struct:pata_icside_state
70 const struct portinfo *port[2]; member in struct:pata_icside_info
117 if (!state->port[0].disabled)
119 if (!state->port[1].disabled)
216 state->port[ap->port_no].speed[adev->devno] = cycle;
234 writeb(state->port[ap->port_no].port_sel, state->ioc_base);
236 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
282 state->port[0].speed[i] = 480;
283 state->port[1].speed[i] = 480;
309 state->port[a
340 pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base, struct pata_icside_info *info, const struct portinfo *port) argument
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H A Dpata_jmicron.c3 * PATA port of the controller. The SATA ports are
34 * Perform the PATA port setup we need.
36 * On the Jmicron 361/363 there is a single PATA port that can be mapped
48 int port = ap->port_no; local
51 /* Check if our port is enabled */
58 SATA port mapped */
67 /* The 365/366 may have this bit set to map the second PATA port
75 port = port ^ 1;
78 * Now we know which physical port w
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H A Dpata_legacy.c2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
80 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
109 unsigned long port; member in struct:legacy_probe
134 static int probe_all; /* Set to check all ISA port ranges */
152 give I/O port if non standard */
155 give I/O port if non standard */
160 * @port: Controller port
169 * An I/O port list is used to keep ordering stable and sane, as we
173 static int legacy_probe_add(unsigned long port, unsigne argument
764 winbond_writecfg(unsigned long port, u8 reg, u8 val) argument
773 winbond_readcfg(unsigned long port, u8 reg) argument
1092 qdi65_identify_port(u8 r, u8 res, unsigned long port) argument
1135 unsigned long port = qd_port[i]; local
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H A Dpata_ns87410.c60 * and only affects the data port.
66 int port = 0x40 + 4 * ap->port_no; local
80 pci_read_config_byte(pdev, port + 3, &idefr);
98 pci_write_config_byte(pdev, port, idetcr);
99 pci_write_config_byte(pdev, port + 3, idefr);
H A Dpata_ns87415.c221 * @port: Port to read
226 static u8 ns87560_read_buggy(void __iomem *port) argument
231 tmp = ioread8(port);
H A Dpata_pdc2027x.c222 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
226 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
231 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
252 /* Check whether port enabled */
674 * @port: ata ioports to setup
677 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) argument
679 port->cmd_addr =
680 port->data_addr = base;
681 port->feature_addr =
682 port
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H A Dpata_pdc202xx_old.c81 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; local
87 pci_read_config_byte(pdev, port, &r_ap);
88 pci_read_config_byte(pdev, port + 1, &r_bp);
98 pci_write_config_byte(pdev, port, r_ap);
99 pci_write_config_byte(pdev, port + 1, r_bp);
128 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; local
144 pci_read_config_byte(pdev, port + 1, &r_bp);
145 pci_read_config_byte(pdev, port + 2, &r_cp);
160 pci_write_config_byte(pdev, port + 1, r_bp);
161 pci_write_config_byte(pdev, port
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H A Dpata_pxa.c219 static void pxa_ata_dma_irq(int dma, void *port) argument
221 struct ata_port *ap = port;
245 * - CMD port base address
246 * - CTL port base address
247 * - DMA port base address
256 * CMD port base address
263 * CTL port base address
270 * DMA port base address
H A Dpata_sch.c113 unsigned int port = adev->devno ? D1TIM : D0TIM; local
116 pci_read_config_dword(dev, port, &data);
124 pci_write_config_dword(dev, port, data);
142 unsigned int port = adev->devno ? D1TIM : D0TIM; local
145 pci_read_config_dword(dev, port, &data);
156 pci_write_config_dword(dev, port, data);
H A Dpata_sis.c81 * Returns the base of the PCI configuration registers for this port
94 * Returns the base of the PCI configuration registers for this port
102 int port = 0x40; local
108 port = 0x70;
110 return port + (8 * ap->port_no) + (4 * adev->devno);
167 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
168 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
229 int port = sis_old_port_base(adev); local
238 pci_read_config_byte(pdev, port, &t1);
239 pci_read_config_byte(pdev, port
266 int port = sis_old_port_base(adev); local
291 int port; local
484 int port; local
531 int port = sis_port_base(adev); local
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H A Dpdc_adma.c120 board_1841_idx = 0, /* ADMA 2-port controller */
533 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) argument
535 port->cmd_addr =
536 port->data_addr = base + 0x000;
537 port->error_addr =
538 port->feature_addr = base + 0x004;
539 port->nsect_addr = base + 0x008;
540 port->lbal_addr = base + 0x00c;
541 port->lbam_addr = base + 0x010;
542 port
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H A Dsata_dwc_460ex.c469 unsigned int port = 0; local
472 ap = host->ports[port];
481 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
482 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
930 * This Interrupt handler called via port ops registered function.
941 int handled, num_processed, port = 0; local
951 ap = host->ports[port];
1262 static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base) argument
1264 port->cmd_addr = (void *)base + 0x00;
1265 port
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H A Dsata_highbank.c100 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, argument
103 return 1 << (3 * pdata->port_to_sgpio[port] + shift);
106 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) argument
109 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
112 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
115 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
118 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
121 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
124 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
182 /* save off new led state for port/slo
343 int phy_count = 0, phy, port = 0, i; local
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H A Dsata_mv.c157 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
160 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
227 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
228 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
250 DMA_IRQ = (1 << 0), /* shift by port # */
252 DEV_IRQ = (1 << 8), /* shift by port # */
513 * We keep a local cache of a few frequently accessed port
870 mv_hc_from_port(unsigned int port) argument
875 mv_hardport_from_port(unsigned int port) argument
903 mv_hc_base_from_port(void __iomem *base, unsigned int port) argument
909 mv_port_base(void __iomem *base, unsigned int port) argument
916 mv5_phy_base(void __iomem *mmio, unsigned int port) argument
1061 unsigned int shift, hardport, port = ap->port_no; local
1288 mv_dump_all_regs(void __iomem *mmio_base, int port, struct pci_dev *pdev) argument
1582 unsigned int port; local
2890 unsigned int handled = 0, port; local
3132 mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3161 mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3206 unsigned int hc, port; local
3344 mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3443 mv_soc_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3484 unsigned int port; local
3505 mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, unsigned int port) argument
3671 unsigned int port = ap->port_no; local
3699 mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) argument
3928 int rc = 0, n_hc, port, hc; local
4062 int port; local
4207 int port; local
4397 int n_ports, port, rc; local
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H A Dsata_qstor.c99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
463 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base) argument
465 port->cmd_addr =
466 port->data_addr = base + 0x400;
467 port->error_addr =
468 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
469 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
470 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
471 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
472 port
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H A Dsata_sil24.c118 PORT_PMP_STATUS = 0x0000, /* port device status offset */
119 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
153 PORT_CS_PORT_RST = (1 << 0), /* port reset */
155 PORT_CS_INIT = (1 << 2), /* port initialize */
160 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
161 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
167 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
427 * Use bits 30-31 of port_flags to encode available port numbers.
480 void __iomem *port = sil24_port_base(dev->link->ap); local
483 writel(PORT_CS_CDB16, port
490 void __iomem *port = sil24_port_base(ap); local
530 void __iomem *port = sil24_port_base(ap); local
555 void __iomem *port = sil24_port_base(ap); local
565 void __iomem *port = sil24_port_base(ap); local
580 void __iomem *port = sil24_port_base(ap); local
608 void __iomem *port = sil24_port_base(ap); local
703 void __iomem *port = sil24_port_base(ap); local
892 void __iomem *port = sil24_port_base(ap); local
956 void __iomem *port = sil24_port_base(ap); local
966 void __iomem *port = sil24_port_base(ap); local
979 void __iomem *port = sil24_port_base(ap); local
1106 void __iomem *port = sil24_port_base(ap); local
1242 void __iomem *port = sil24_port_base(ap); local
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H A Dsata_svw.c340 /* Match it to a port node */
414 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) argument
416 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
417 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
418 port->feature_addr =
419 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
420 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
421 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
422 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
423 port
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H A Dsata_sx4.c38 engine, DIMM memory, and four ATA engines (one per SATA port).
978 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base) argument
980 port->cmd_addr = base;
981 port->data_addr = base;
982 port->feature_addr =
983 port->error_addr = base + 0x4;
984 port->nsect_addr = base + 0x8;
985 port->lbal_addr = base + 0xc;
986 port->lbam_addr = base + 0x10;
987 port
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H A Dsata_via.c428 static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port) argument
430 return addr + (port * 128);
433 static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port) argument
435 return addr + (port * 64);
454 ata_port_pbar_desc(ap, ap->port_no, -1, "port");

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