Searched defs:reset (Results 1 - 25 of 181) sorted by path

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/drivers/ata/
H A Dlibata-eh.c97 * the first reset w/ 10sec timeout should succeed. Following entries
99 * take an exceptionally long time to recover from reset.
1113 * thawed, which usually follows a successful reset.
2139 /* SError read failed, force reset and probing */
2588 static int ata_do_reset(struct ata_link *link, ata_reset_fn_t reset, argument
2598 return reset(link, classes, deadline);
2627 ata_reset_fn_t reset; local
2633 * Prepare to reset
2644 /* make sure each reset attempt is at least COOL_DOWN apart */
2663 * we do a hard reset (o
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/drivers/atm/
H A Dfore200e.h257 OPCODE_RESET_STATS, /* reset board statistics */
815 void (*reset)(struct fore200e*); member in struct:fore200e_bus
H A Dsolos-pci.c86 static int reset = 0; variable
158 MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
164 module_param(reset, int, 0444);
1238 if (reset) {
1452 /* Release device from reset */
/drivers/block/
H A Dhd.c115 static int reset; variable
318 if (reset)
321 reset = 1;
348 dump_status("reset timed out", c);
363 printk("hd: controller reset failed: %02x\n", hd_error);
371 if (reset) {
372 reset = 0;
377 if (reset)
385 if (reset)
393 * doing a reset an
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/drivers/block/rsxx/
H A Drsxx_priv.h151 int reset; member in struct:rsxx_cardinfo::__anon366
/drivers/bluetooth/
H A Dbtusb.c36 static bool reset = 1; variable
1252 /* Clear the reset quirk since this is not an actual
1505 * As a workaround, send HCI Reset command first which will reset the
1511 BT_ERR("%s sending initial HCI reset command failed (%ld)",
1614 * the manufacturer mode is disabled with reset and activating the
1618 * disabled with reset and deactivating the patch.
1620 * If the default patch file is used, no reset is done when disabling
1638 * with reset and activate the downloaded firmware patches.
1656 /* Disable the manufacturer mode without reset */
1674 /* Patching failed. Disable the manufacturer mode with reset an
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/drivers/char/
H A Dlp.c50 * lp=reset (reset the printer during
62 * # insmod lp.o reset=1
833 static bool reset; variable
836 module_param(reset, bool, 0);
863 } else if (!strcmp(str, "reset")) {
864 reset = 1;
879 if (reset)
/drivers/char/xilinx_hwicap/
H A Dxilinx_hwicap.h85 void (*reset)(struct hwicap_drvdata *drvdata); member in struct:hwicap_driver_config
/drivers/clk/
H A Dclk-u300.c425 * @reset: state holder, whether this block's reset line is asserted or not
426 * @res_reg: reset line enable/disable flag register
427 * @res_bit: bit for resetting or taking this consumer out of reset
436 bool reset; member in struct:clk_syscon
450 * taken out of reset and don't remove the reset assertion again
467 sclk->reset = true;
483 sclk->reset = false;
490 /* If the block is in reset, brin
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/drivers/clk/qcom/
H A Dcommon.c18 #include <linux/reset-controller.h>
23 #include "reset.h"
26 struct qcom_reset_controller reset; member in struct:qcom_cc
70 struct qcom_reset_controller *reset; local
100 reset = &cc->reset;
101 reset->rcdev.of_node = dev->of_node;
102 reset->rcdev.ops = &qcom_reset_ops;
103 reset->rcdev.owner = dev->driver->owner;
104 reset
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/drivers/crypto/caam/
H A Dregs.h31 * For example, let's assume a SW reset of CAAM through the master
40 * Assuming a 64-bit write to this MCFG to perform a software reset
43 * reset.
46 * write 0x8000000 to base+0x0004, and the reset would work fine.
243 u32 reset; /* RTSTRESETx - Test reset control */ member in struct:rngtst
325 #define DECO_RESET 1 /* Use with DECO reset/availability regs */
355 u32 deco_reset; /* DRR - DECO reset */
383 #define MCFGR_SWRESET 0x80000000 /* software reset */
/drivers/crypto/
H A Dhifn_795x.c204 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
314 /* Public key reset register (HIFN_1_PUB_RESET) */
315 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
444 unsigned long reset; member in struct:hifn_device
707 dprintk("%s: Failed to reset PUC unit.\n", dev->name);
1834 dev->reset = 0;
1888 int reset = 0; local
1917 reset = 1;
1921 if (reset) {
1922 if (++dev->reset >
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/drivers/dma/
H A Dmxs-dma.c122 bool reset; member in struct:mxs_dma_chan
212 * channel stall, we have to reset the whole DMA engine. To avoid this,
214 * mxs_dma_int_handler. To reset the channel, we can simply stop writing
219 mxs_chan->reset = true;
230 * On i.MX28 APBX, the DMA channel can stop working if we reset
233 * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
243 "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
272 mxs_chan->reset = false;
399 if (mxs_chan->reset)
/drivers/firewire/
H A Dcore-cdev.c176 struct fw_cdev_event_bus_reset reset; member in struct:bus_reset_event
396 fill_bus_reset_event(&e->reset, client);
399 &e->reset, sizeof(e->reset), NULL, 0);
/drivers/gpio/
H A Dgpio-pch.c48 u32 reset; member in struct:pch_regs
507 iowrite32(0x01, &chip->reg->reset);
508 iowrite32(0x00, &chip->reg->reset);
/drivers/gpu/drm/exynos/
H A Dexynos_drm_ipp.h153 * @reset: reset ipp block.
173 int (*reset)(struct device *dev); member in struct:exynos_drm_ippdrv
/drivers/gpu/drm/gma500/
H A Dmdfld_output.h58 int (*reset)(int pipe); member in struct:panel_funcs
/drivers/gpu/drm/i915/
H A Di915_drv.h604 /* Time when this context was last blamed for a GPU reset */
1202 /* For reset and error_state handling. */
1212 * State variable controlling the reset flow and count
1214 * This is a counter which gets incremented when reset is triggered,
1215 * and again when reset has been handled. So odd values (lowest bit set)
1216 * means that reset is in progress and even values that
1217 * (reset_counter >> 1):th reset was successfully completed.
1219 * If reset is not completed succesfully, the I915_WEDGE bit is
1224 * This counter is used by the wait_seqno code to notice that reset
1230 * waiter and the gpu reset wor
2221 bool reset; member in struct:i915_params
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/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.h137 void (*reset)(struct hdmi_phy *phy); member in struct:hdmi_phy_funcs
/drivers/gpu/drm/nouveau/core/include/subdev/
H A Dgpio.h28 void (*reset)(struct nouveau_gpio *, u8 func); member in struct:nouveau_gpio
/drivers/gpu/drm/nouveau/core/subdev/gpio/
H A Dpriv.h52 void (*reset)(struct nouveau_gpio *, u8); member in struct:nouveau_gpio_impl
/drivers/gpu/drm/sti/
H A Dsti_hdmi.h44 * @reset: reset control of the hdmi phy
64 struct reset_control *reset; member in struct:sti_hdmi
H A Dsti_tvout.c14 #include <linux/reset.h>
111 struct reset_control *reset; member in struct:sti_tvout
402 /* reset VIP register */
454 /* reset VIP register */
597 /* get reset resources */
598 tvout->reset = devm_reset_control_get(dev, "tvout");
599 /* take tvout out of reset */
600 if (!IS_ERR(tvout->reset))
601 reset_control_deassert(tvout->reset);
/drivers/hid/
H A Dhid-picolcd.h158 struct hid_report *reset);
174 struct hid_report *reset)
171 picolcd_init_devfs(struct picolcd_data *data, struct hid_report *eeprom_r, struct hid_report *eeprom_w, struct hid_report *flash_r, struct hid_report *flash_w, struct hid_report *reset) argument
H A Dhid-picolcd_debugfs.c450 /* 2 data bytes with reset duration in ms */
850 struct hid_report *reset)
856 /* reset */
857 if (reset)
858 data->debug_reset = debugfs_create_file("reset", 0600,
847 picolcd_init_devfs(struct picolcd_data *data, struct hid_report *eeprom_r, struct hid_report *eeprom_w, struct hid_report *flash_r, struct hid_report *flash_w, struct hid_report *reset) argument

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