11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/arch/alpha/kernel/pci_impl.h 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This file contains declarations and inline functions for interfacing 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * with the PCI initialization routines. 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct pci_dev; 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct pci_controller; 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct pci_iommu_arena; 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We can't just blindly use 64K for machines with EISA busses; they 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * may also have PCI-PCI bridges present, and then we'd configure the 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * bridge incorrectly. 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Also, we start at 0x8000 or 0x9000, in hopes to get all devices' 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * IO space areas allocated *before* 0xC000; this is because certain 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * BIOSes (Millennium for one) use PCI Config space "mechanism #2" 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * accesses to probe the bus. If a device's registers appear at 0xC000, 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it may see an INx/OUTx at that address during BIOS emulation of the 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense. 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */ 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */ 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We try to make the DEFAULT_MEM_BASE addresses *always* have more than 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a single bit set. This is so that devices like the broken Myrinet card 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * will always have a PCI memory address that will never match a IDSEL 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address in PCI Config space, which can cause problems with early rev cards. 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * that get passed through the PCI<->ISA bridge chip. Although this causes 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * us to set the PCI->Mem window bases lower than normal, we still allocate 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PCI bus devices' memory addresses *below* the low DMA mapping window, 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * and hope they fit below 64Mb (to avoid conflicts), and so that they can 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * be accessed via SPARSE space. 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We accept the risk that a broken Myrinet card will be put into a true XL 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * and thus can more easily run into the problem described below. 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * bus memory addresses for SPARSE access to be less than 128Mb. 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024) 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Because MCPCIA and T2 core logic support more bits for 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * physical addresses, they should allow an expanded range of SPARSE 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * memory addresses. However, we do not use them all, in order to 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * avoid the HAE manipulation that would be needed. 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024) 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024) 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Because CIA and PYXIS have more bits for physical addresses, 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * they support an expanded range of SPARSE memory addresses. 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEFAULT_MEM_BASE ((128+16)*1024*1024) 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ??? Experimenting with no HAE for CIA. */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024) 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024) 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DEFAULT_AGP_APER_SIZE (64*1024*1024) 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * A small note about bridges and interrupts. The DECchip 21050 (and 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * later) adheres to the PCI-PCI bridge specification. This says that 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the interrupts on the other side of a bridge are swizzled in the 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * following manner: 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Dev Interrupt Interrupt 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Pin on Pin on 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Device Connector 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4 A A 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * B B 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * C C 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * D D 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5 A B 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * B C 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * C D 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * D A 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 6 A C 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * B D 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * C A 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * D B 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 7 A D 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * B A 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * C B 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * D C 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1091be9baa09340bbe3329aab3bd0d41076f59c8f22Bjorn Helgaas * pci_swizzle_interrupt_pin() swizzles for exactly one bridge. The routine 1103e08601f7f9b497abcb383491058bfb9e1dc6ec9Bjorn Helgaas * pci_common_swizzle() handles multiple bridges. But there are a 1111be9baa09340bbe3329aab3bd0d41076f59c8f22Bjorn Helgaas * couple boards that do strange things. 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The following macro is used to implement the table-based irq mapping 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds function for all single-bus Alphas. */ 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define COMMON_TABLE_LOOKUP \ 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds({ long _ctl_ = -1; \ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot) \ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds _ctl_ = irq_tab[slot - min_idsel][pin]; \ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds _ctl_; }) 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* A PCI IOMMU allocation arena. There are typically two of these 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds regions per bus. */ 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ??? The 8400 has a 32-byte pte entry, and the entire table apparently 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds lives directly on the host bridge (no tlb?). We don't support this 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds machine, but if we ever did, we'd need to parameterize all this quite 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds a bit further. Probably with per-bus operation tables. */ 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct pci_iommu_arena 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds spinlock_t lock; 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_controller *hose; 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */ 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IOMMU_RESERVED_PTE 0xface 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long *ptes; 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t dma_base; 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int size; 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int next_entry; 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int align_entry; 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if defined(CONFIG_ALPHA_SRM) && \ 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA)) 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds# define NEED_SRM_SAVE_RESTORE 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds# undef NEED_SRM_SAVE_RESTORE 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if defined(CONFIG_ALPHA_GENERIC) || defined(NEED_SRM_SAVE_RESTORE) 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds# define ALPHA_RESTORE_SRM_SETUP 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds# undef ALPHA_RESTORE_SRM_SETUP 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef ALPHA_RESTORE_SRM_SETUP 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Store PCI device configuration left by SRM here. */ 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct pdev_srm_saved_conf 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pdev_srm_saved_conf *next; 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_dev *dev; 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern void pci_restore_srm_config(void); 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define pdev_save_srm_config(dev) do {} while (0) 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define pci_restore_srm_config() do {} while (0) 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The hose list. */ 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern struct pci_controller *hose_head, **hose_tail; 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern struct pci_controller *pci_isa_hose; 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern unsigned long alpha_agpgart_size; 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern void common_init_pci(void); 1793e08601f7f9b497abcb383491058bfb9e1dc6ec9Bjorn Helgaas#define common_swizzle pci_common_swizzle 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern struct pci_controller *alloc_pci_controller(void); 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern struct resource *alloc_resource(void); 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern struct pci_iommu_arena *iommu_arena_new_node(int, 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct pci_controller *, 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t, unsigned long, 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long); 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern struct pci_iommu_arena *iommu_arena_new(struct pci_controller *, 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t, unsigned long, 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long); 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern const char *const pci_io_names[]; 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern const char *const pci_mem_names[]; 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern const char pci_hae0_name[]; 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern unsigned long size_for_memory(unsigned long max); 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern int iommu_reserve(struct pci_iommu_arena *, long, long); 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern int iommu_release(struct pci_iommu_arena *, long, long); 198d68721eb339e9237c11c1fea5f73f86211d14918Ivan Kokshayskyextern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **); 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsextern int iommu_unbind(struct pci_iommu_arena *, long, long); 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 202