1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 * 12 * Contains definitions specific to the Armada XP MV78230 SoC that are not 13 * common to all Armada XP SoCs. 14 */ 15 16#include "armada-xp.dtsi" 17 18/ { 19 model = "Marvell Armada XP MV78230 SoC"; 20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 enable-method = "marvell,armada-xp-smp"; 31 32 cpu@0 { 33 device_type = "cpu"; 34 compatible = "marvell,sheeva-v7"; 35 reg = <0>; 36 clocks = <&cpuclk 0>; 37 clock-latency = <1000000>; 38 }; 39 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "marvell,sheeva-v7"; 43 reg = <1>; 44 clocks = <&cpuclk 1>; 45 clock-latency = <1000000>; 46 }; 47 }; 48 49 soc { 50 /* 51 * MV78230 has 2 PCIe units Gen2.0: One unit can be 52 * configured as x4 or quad x1 lanes. One unit is 53 * x1 only. 54 */ 55 pcie-controller { 56 compatible = "marvell,armada-xp-pcie"; 57 status = "disabled"; 58 device_type = "pci"; 59 60 #address-cells = <3>; 61 #size-cells = <2>; 62 63 msi-parent = <&mpic>; 64 bus-range = <0x00 0xff>; 65 66 ranges = 67 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 68 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 69 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 70 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 71 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 72 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 73 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 74 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 75 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 76 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 77 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 78 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 79 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 80 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 81 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 82 83 pcie@1,0 { 84 device_type = "pci"; 85 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 86 reg = <0x0800 0 0 0 0>; 87 #address-cells = <3>; 88 #size-cells = <2>; 89 #interrupt-cells = <1>; 90 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 91 0x81000000 0 0 0x81000000 0x1 0 1 0>; 92 interrupt-map-mask = <0 0 0 0>; 93 interrupt-map = <0 0 0 0 &mpic 58>; 94 marvell,pcie-port = <0>; 95 marvell,pcie-lane = <0>; 96 clocks = <&gateclk 5>; 97 status = "disabled"; 98 }; 99 100 pcie@2,0 { 101 device_type = "pci"; 102 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 103 reg = <0x1000 0 0 0 0>; 104 #address-cells = <3>; 105 #size-cells = <2>; 106 #interrupt-cells = <1>; 107 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 108 0x81000000 0 0 0x81000000 0x2 0 1 0>; 109 interrupt-map-mask = <0 0 0 0>; 110 interrupt-map = <0 0 0 0 &mpic 59>; 111 marvell,pcie-port = <0>; 112 marvell,pcie-lane = <1>; 113 clocks = <&gateclk 6>; 114 status = "disabled"; 115 }; 116 117 pcie@3,0 { 118 device_type = "pci"; 119 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 120 reg = <0x1800 0 0 0 0>; 121 #address-cells = <3>; 122 #size-cells = <2>; 123 #interrupt-cells = <1>; 124 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 125 0x81000000 0 0 0x81000000 0x3 0 1 0>; 126 interrupt-map-mask = <0 0 0 0>; 127 interrupt-map = <0 0 0 0 &mpic 60>; 128 marvell,pcie-port = <0>; 129 marvell,pcie-lane = <2>; 130 clocks = <&gateclk 7>; 131 status = "disabled"; 132 }; 133 134 pcie@4,0 { 135 device_type = "pci"; 136 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 137 reg = <0x2000 0 0 0 0>; 138 #address-cells = <3>; 139 #size-cells = <2>; 140 #interrupt-cells = <1>; 141 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 142 0x81000000 0 0 0x81000000 0x4 0 1 0>; 143 interrupt-map-mask = <0 0 0 0>; 144 interrupt-map = <0 0 0 0 &mpic 61>; 145 marvell,pcie-port = <0>; 146 marvell,pcie-lane = <3>; 147 clocks = <&gateclk 8>; 148 status = "disabled"; 149 }; 150 151 pcie@5,0 { 152 device_type = "pci"; 153 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 154 reg = <0x2800 0 0 0 0>; 155 #address-cells = <3>; 156 #size-cells = <2>; 157 #interrupt-cells = <1>; 158 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 159 0x81000000 0 0 0x81000000 0x5 0 1 0>; 160 interrupt-map-mask = <0 0 0 0>; 161 interrupt-map = <0 0 0 0 &mpic 62>; 162 marvell,pcie-port = <1>; 163 marvell,pcie-lane = <0>; 164 clocks = <&gateclk 9>; 165 status = "disabled"; 166 }; 167 }; 168 169 internal-regs { 170 pinctrl { 171 compatible = "marvell,mv78230-pinctrl"; 172 reg = <0x18000 0x38>; 173 174 sdio_pins: sdio-pins { 175 marvell,pins = "mpp30", "mpp31", "mpp32", 176 "mpp33", "mpp34", "mpp35"; 177 marvell,function = "sd0"; 178 }; 179 }; 180 181 gpio0: gpio@18100 { 182 compatible = "marvell,orion-gpio"; 183 reg = <0x18100 0x40>; 184 ngpios = <32>; 185 gpio-controller; 186 #gpio-cells = <2>; 187 interrupt-controller; 188 #interrupt-cells = <2>; 189 interrupts = <82>, <83>, <84>, <85>; 190 }; 191 192 gpio1: gpio@18140 { 193 compatible = "marvell,orion-gpio"; 194 reg = <0x18140 0x40>; 195 ngpios = <17>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 interrupts = <87>, <88>, <89>; 201 }; 202 }; 203 }; 204}; 205