1/* 2 * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) 3 * 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include "omap3-igep.dtsi" 13#include "omap-gpmc-smsc9221.dtsi" 14 15/ { 16 model = "IGEPv2 (TI OMAP AM/DM37x)"; 17 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; 18 19 leds { 20 pinctrl-names = "default"; 21 pinctrl-0 = <&leds_pins>; 22 compatible = "gpio-leds"; 23 24 boot { 25 label = "omap3:green:boot"; 26 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 27 default-state = "on"; 28 }; 29 30 user0 { 31 label = "omap3:red:user0"; 32 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; 33 default-state = "off"; 34 }; 35 36 user1 { 37 label = "omap3:red:user1"; 38 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 39 default-state = "off"; 40 }; 41 42 user2 { 43 label = "omap3:green:user1"; 44 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; 45 }; 46 }; 47 48 /* HS USB Port 1 Power */ 49 hsusb1_power: hsusb1_power_reg { 50 compatible = "regulator-fixed"; 51 regulator-name = "hsusb1_vbus"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ 55 startup-delay-us = <70000>; 56 }; 57 58 /* HS USB Host PHY on PORT 1 */ 59 hsusb1_phy: hsusb1_phy { 60 compatible = "usb-nop-xceiv"; 61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ 62 vcc-supply = <&hsusb1_power>; 63 }; 64 65 tfp410: encoder@0 { 66 compatible = "ti,tfp410"; 67 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ 68 69 ports { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 port@0 { 74 reg = <0>; 75 76 tfp410_in: endpoint@0 { 77 remote-endpoint = <&dpi_out>; 78 }; 79 }; 80 81 port@1 { 82 reg = <1>; 83 84 tfp410_out: endpoint@0 { 85 remote-endpoint = <&dvi_connector_in>; 86 }; 87 }; 88 }; 89 }; 90 91 dvi0: connector@0 { 92 compatible = "dvi-connector"; 93 label = "dvi"; 94 95 digital; 96 97 ddc-i2c-bus = <&i2c3>; 98 99 port { 100 dvi_connector_in: endpoint { 101 remote-endpoint = <&tfp410_out>; 102 }; 103 }; 104 }; 105}; 106 107&omap3_pmx_core { 108 pinctrl-names = "default"; 109 pinctrl-0 = < 110 &tfp410_pins 111 &dss_dpi_pins 112 >; 113 114 tfp410_pins: pinmux_tfp410_pins { 115 pinctrl-single,pins = < 116 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 117 >; 118 }; 119 120 dss_dpi_pins: pinmux_dss_dpi_pins { 121 pinctrl-single,pins = < 122 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 123 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 124 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 125 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 126 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 127 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 128 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 129 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 130 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 131 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 132 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 133 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 134 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 135 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 136 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 137 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 138 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 139 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 140 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 141 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 142 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 143 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 144 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 145 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 146 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 147 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 148 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 149 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 150 >; 151 }; 152}; 153 154&omap3_pmx_core2 { 155 pinctrl-names = "default"; 156 pinctrl-0 = < 157 &hsusbb1_pins 158 >; 159 160 hsusbb1_pins: pinmux_hsusbb1_pins { 161 pinctrl-single,pins = < 162 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ 163 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ 164 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ 165 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ 166 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ 167 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ 168 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ 169 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ 170 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ 171 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ 172 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ 173 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ 174 >; 175 }; 176 177 leds_pins: pinmux_leds_pins { 178 pinctrl-single,pins = < 179 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ 180 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ 181 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ 182 >; 183 }; 184}; 185 186&i2c3 { 187 clock-frequency = <100000>; 188 189 /* 190 * Display monitor features are burnt in the EEPROM 191 * as EDID data. 192 */ 193 eeprom@50 { 194 compatible = "ti,eeprom"; 195 reg = <0x50>; 196 }; 197}; 198 199&gpmc { 200 ranges = <0 0 0x00000000 0x20000000>, 201 <5 0 0x2c000000 0x01000000>; 202 203 nand@0,0 { 204 linux,mtd-name= "micron,mt29c4g96maz"; 205 reg = <0 0 0>; 206 nand-bus-width = <16>; 207 ti,nand-ecc-opt = "bch8"; 208 209 gpmc,sync-clk-ps = <0>; 210 gpmc,cs-on-ns = <0>; 211 gpmc,cs-rd-off-ns = <44>; 212 gpmc,cs-wr-off-ns = <44>; 213 gpmc,adv-on-ns = <6>; 214 gpmc,adv-rd-off-ns = <34>; 215 gpmc,adv-wr-off-ns = <44>; 216 gpmc,we-off-ns = <40>; 217 gpmc,oe-off-ns = <54>; 218 gpmc,access-ns = <64>; 219 gpmc,rd-cycle-ns = <82>; 220 gpmc,wr-cycle-ns = <82>; 221 gpmc,wr-access-ns = <40>; 222 gpmc,wr-data-mux-bus-ns = <0>; 223 224 #address-cells = <1>; 225 #size-cells = <1>; 226 227 partition@0 { 228 label = "SPL"; 229 reg = <0 0x100000>; 230 }; 231 partition@80000 { 232 label = "U-Boot"; 233 reg = <0x100000 0x180000>; 234 }; 235 partition@1c0000 { 236 label = "Environment"; 237 reg = <0x280000 0x100000>; 238 }; 239 partition@280000 { 240 label = "Kernel"; 241 reg = <0x380000 0x300000>; 242 }; 243 partition@780000 { 244 label = "Filesystem"; 245 reg = <0x680000 0x1f980000>; 246 }; 247 }; 248 249 ethernet@gpmc { 250 pinctrl-names = "default"; 251 pinctrl-0 = <&smsc9221_pins>; 252 reg = <5 0 0xff>; 253 interrupt-parent = <&gpio6>; 254 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 255 }; 256}; 257 258&usbhshost { 259 port1-mode = "ehci-phy"; 260}; 261 262&usbhsehci { 263 phys = <&hsusb1_phy>; 264}; 265 266&vpll2 { 267 /* Needed for DSS */ 268 regulator-name = "vdds_dsi"; 269}; 270 271&dss { 272 status = "ok"; 273 274 port { 275 dpi_out: endpoint { 276 remote-endpoint = <&tfp410_in>; 277 data-lines = <24>; 278 }; 279 }; 280}; 281