1/*
2 *  linux/arch/arm/kernel/irq.c
3 *
4 *  Copyright (C) 1992 Linus Torvalds
5 *  Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
6 *
7 *  Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
8 *  Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and
9 *  Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 *  This file contains the code used by various IRQ handling routines:
16 *  asking for different IRQ's should be done through these routines
17 *  instead of just grabbing them. Thus setups with different IRQ numbers
18 *  shouldn't result in any weird surprises, and installing new handlers
19 *  should be easier.
20 *
21 *  IRQ's are in fact implemented a bit like signal handlers for the kernel.
22 *  Naturally it's not a 1:1 relation, but there are similarities.
23 */
24#include <linux/kernel_stat.h>
25#include <linux/signal.h>
26#include <linux/ioport.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/irqchip.h>
30#include <linux/random.h>
31#include <linux/smp.h>
32#include <linux/init.h>
33#include <linux/seq_file.h>
34#include <linux/errno.h>
35#include <linux/list.h>
36#include <linux/kallsyms.h>
37#include <linux/proc_fs.h>
38#include <linux/export.h>
39
40#include <asm/hardware/cache-l2x0.h>
41#include <asm/exception.h>
42#include <asm/mach/arch.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/time.h>
45
46unsigned long irq_err_count;
47
48int arch_show_interrupts(struct seq_file *p, int prec)
49{
50#ifdef CONFIG_FIQ
51	show_fiq_list(p, prec);
52#endif
53#ifdef CONFIG_SMP
54	show_ipi_list(p, prec);
55#endif
56	seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
57	return 0;
58}
59
60/*
61 * handle_IRQ handles all hardware IRQ's.  Decoded IRQs should
62 * not come via this function.  Instead, they should provide their
63 * own 'handler'.  Used by platform code implementing C-based 1st
64 * level decoding.
65 */
66void handle_IRQ(unsigned int irq, struct pt_regs *regs)
67{
68	__handle_domain_irq(NULL, irq, false, regs);
69}
70
71/*
72 * asm_do_IRQ is the interface to be used from assembly code.
73 */
74asmlinkage void __exception_irq_entry
75asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
76{
77	handle_IRQ(irq, regs);
78}
79
80void set_irq_flags(unsigned int irq, unsigned int iflags)
81{
82	unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
83
84	if (irq >= nr_irqs) {
85		printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
86		return;
87	}
88
89	if (iflags & IRQF_VALID)
90		clr |= IRQ_NOREQUEST;
91	if (iflags & IRQF_PROBE)
92		clr |= IRQ_NOPROBE;
93	if (!(iflags & IRQF_NOAUTOEN))
94		clr |= IRQ_NOAUTOEN;
95	/* Order is clear bits in "clr" then set bits in "set" */
96	irq_modify_status(irq, clr, set & ~clr);
97}
98EXPORT_SYMBOL_GPL(set_irq_flags);
99
100void __init init_IRQ(void)
101{
102	int ret;
103
104	if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
105		irqchip_init();
106	else
107		machine_desc->init_irq();
108
109	if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
110	    (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
111		outer_cache.write_sec = machine_desc->l2c_write_sec;
112		ret = l2x0_of_init(machine_desc->l2c_aux_val,
113				   machine_desc->l2c_aux_mask);
114		if (ret)
115			pr_err("L2C: failed to init: %d\n", ret);
116	}
117}
118
119#ifdef CONFIG_MULTI_IRQ_HANDLER
120void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
121{
122	if (handle_arch_irq)
123		return;
124
125	handle_arch_irq = handle_irq;
126}
127#endif
128
129#ifdef CONFIG_SPARSE_IRQ
130int __init arch_probe_nr_irqs(void)
131{
132	nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
133	return nr_irqs;
134}
135#endif
136
137#ifdef CONFIG_HOTPLUG_CPU
138
139static bool migrate_one_irq(struct irq_desc *desc)
140{
141	struct irq_data *d = irq_desc_get_irq_data(desc);
142	const struct cpumask *affinity = d->affinity;
143	struct irq_chip *c;
144	bool ret = false;
145
146	/*
147	 * If this is a per-CPU interrupt, or the affinity does not
148	 * include this CPU, then we have nothing to do.
149	 */
150	if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
151		return false;
152
153	if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
154		affinity = cpu_online_mask;
155		ret = true;
156	}
157
158	c = irq_data_get_irq_chip(d);
159	if (!c->irq_set_affinity)
160		pr_debug("IRQ%u: unable to set affinity\n", d->irq);
161	else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
162		cpumask_copy(d->affinity, affinity);
163
164	return ret;
165}
166
167/*
168 * The current CPU has been marked offline.  Migrate IRQs off this CPU.
169 * If the affinity settings do not allow other CPUs, force them onto any
170 * available CPU.
171 *
172 * Note: we must iterate over all IRQs, whether they have an attached
173 * action structure or not, as we need to get chained interrupts too.
174 */
175void migrate_irqs(void)
176{
177	unsigned int i;
178	struct irq_desc *desc;
179	unsigned long flags;
180
181	local_irq_save(flags);
182
183	for_each_irq_desc(i, desc) {
184		bool affinity_broken;
185
186		raw_spin_lock(&desc->lock);
187		affinity_broken = migrate_one_irq(desc);
188		raw_spin_unlock(&desc->lock);
189
190		if (affinity_broken && printk_ratelimit())
191			pr_warn("IRQ%u no longer affine to CPU%u\n",
192				i, smp_processor_id());
193	}
194
195	local_irq_restore(flags);
196}
197#endif /* CONFIG_HOTPLUG_CPU */
198