1/* 2 * Copyright 2008 Cavium Networks 3 * 4 * This file is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, Version 2, as 6 * published by the Free Software Foundation. 7 */ 8 9#ifndef __MACH_BOARD_CNS3XXXH 10#define __MACH_BOARD_CNS3XXXH 11 12/* 13 * Memory map 14 */ 15#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ 16#define CNS3XXX_FLASH_SIZE SZ_256M 17 18#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ 19 20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ 21 22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ 23 24#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ 25 26#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ 27 28#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ 29 30#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ 31 32#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ 33 34#define SMC_MEMC_STATUS_OFFSET 0x000 35#define SMC_MEMIF_CFG_OFFSET 0x004 36#define SMC_MEMC_CFG_SET_OFFSET 0x008 37#define SMC_MEMC_CFG_CLR_OFFSET 0x00C 38#define SMC_DIRECT_CMD_OFFSET 0x010 39#define SMC_SET_CYCLES_OFFSET 0x014 40#define SMC_SET_OPMODE_OFFSET 0x018 41#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 42#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 43#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 44#define SMC_NAND_CYCLES0_0_OFFSET 0x100 45#define SMC_OPMODE0_0_OFFSET 0x104 46#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 47#define SMC_NAND_CYCLES0_1_OFFSET 0x120 48#define SMC_OPMODE0_1_OFFSET 0x124 49#define SMC_USER_STATUS_OFFSET 0x200 50#define SMC_USER_CONFIG_OFFSET 0x204 51#define SMC_ECC_STATUS_OFFSET 0x300 52#define SMC_ECC_MEMCFG_OFFSET 0x304 53#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 54#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C 55#define SMC_ECC_ADDR0_OFFSET 0x310 56#define SMC_ECC_ADDR1_OFFSET 0x314 57#define SMC_ECC_VALUE0_OFFSET 0x318 58#define SMC_ECC_VALUE1_OFFSET 0x31C 59#define SMC_ECC_VALUE2_OFFSET 0x320 60#define SMC_ECC_VALUE3_OFFSET 0x324 61#define SMC_PERIPH_ID_0_OFFSET 0xFE0 62#define SMC_PERIPH_ID_1_OFFSET 0xFE4 63#define SMC_PERIPH_ID_2_OFFSET 0xFE8 64#define SMC_PERIPH_ID_3_OFFSET 0xFEC 65#define SMC_PCELL_ID_0_OFFSET 0xFF0 66#define SMC_PCELL_ID_1_OFFSET 0xFF4 67#define SMC_PCELL_ID_2_OFFSET 0xFF8 68#define SMC_PCELL_ID_3_OFFSET 0xFFC 69 70#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ 71 72#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ 73 74#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ 75 76#define RTC_SEC_OFFSET 0x00 77#define RTC_MIN_OFFSET 0x04 78#define RTC_HOUR_OFFSET 0x08 79#define RTC_DAY_OFFSET 0x0C 80#define RTC_SEC_ALM_OFFSET 0x10 81#define RTC_MIN_ALM_OFFSET 0x14 82#define RTC_HOUR_ALM_OFFSET 0x18 83#define RTC_REC_OFFSET 0x1C 84#define RTC_CTRL_OFFSET 0x20 85#define RTC_INTR_STS_OFFSET 0x34 86 87#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ 88#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ 89 90#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ 91#define CNS3XXX_PM_BASE_VIRT 0xFB001000 92 93#define PM_CLK_GATE_OFFSET 0x00 94#define PM_SOFT_RST_OFFSET 0x04 95#define PM_HS_CFG_OFFSET 0x08 96#define PM_CACTIVE_STA_OFFSET 0x0C 97#define PM_PWR_STA_OFFSET 0x10 98#define PM_SYS_CLK_CTRL_OFFSET 0x14 99#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 100#define PM_PLL_HM_PD_OFFSET 0x1C 101 102#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ 103#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 104 105#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ 106 107#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ 108 109#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ 110 111#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ 112 113#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ 114 115#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ 116 117#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ 118#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 119 120#define TIMER1_COUNTER_OFFSET 0x00 121#define TIMER1_AUTO_RELOAD_OFFSET 0x04 122#define TIMER1_MATCH_V1_OFFSET 0x08 123#define TIMER1_MATCH_V2_OFFSET 0x0C 124 125#define TIMER2_COUNTER_OFFSET 0x10 126#define TIMER2_AUTO_RELOAD_OFFSET 0x14 127#define TIMER2_MATCH_V1_OFFSET 0x18 128#define TIMER2_MATCH_V2_OFFSET 0x1C 129 130#define TIMER1_2_CONTROL_OFFSET 0x30 131#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 132#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 133 134#define TIMER_FREERUN_OFFSET 0x40 135#define TIMER_FREERUN_CONTROL_OFFSET 0x44 136 137#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ 138 139#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ 140 141#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ 142 143#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ 144 145#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ 146 147#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ 148 149#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ 150#define CNS3XXX_SATA2_SIZE SZ_16M 151 152#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ 153 154#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ 155 156#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ 157 158#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ 159 160#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ 161 162#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ 163 164#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ 165#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 166 167#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ 168#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 169 170#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ 171#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 172 173#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ 174#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 175 176#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ 177#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 178 179#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ 180#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 181 182#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ 183#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 184 185#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ 186#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 187 188#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ 189#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 190 191#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ 192#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 193 194#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ 195#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 196 197#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ 198#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 199 200/* 201 * Testchip peripheral and fpga gic regions 202 */ 203#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ 204#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 205 206#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ 207#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) 208 209#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 210#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) 211 212#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ 213#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) 214 215#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ 216 217/* 218 * Misc block 219 */ 220#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) 221 222#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) 223#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) 224#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) 225#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) 226#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) 227#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) 228#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) 229#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) 230#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) 231#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) 232#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) 233#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) 234#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) 235#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) 236#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) 237#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) 238#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) 239#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) 240#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) 241#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) 242 243#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) 244 245#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) 246#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) 247#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) 248#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) 249#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) 250#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) 251 252#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) 253#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) 254#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) 255#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) 256#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) 257#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) 258#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) 259#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) 260#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) 261#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) 262#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) 263#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) 264#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) 265#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) 266#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) 267#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) 268#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) 269 270/* 271 * Power management and clock control 272 */ 273#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) 274 275#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) 276#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) 277#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) 278#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) 279#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) 280#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) 281#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) 282#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) 283#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) 284#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) 285#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) 286#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) 287#define PM_CSR_REG PMU_MEM_MAP(0x030) 288 289/* PM_CLK_GATE_REG */ 290#define PM_CLK_GATE_REG_OFFSET_SDIO (25) 291#define PM_CLK_GATE_REG_OFFSET_GPU (24) 292#define PM_CLK_GATE_REG_OFFSET_CIM (23) 293#define PM_CLK_GATE_REG_OFFSET_LCDC (22) 294#define PM_CLK_GATE_REG_OFFSET_I2S (21) 295#define PM_CLK_GATE_REG_OFFSET_RAID (20) 296#define PM_CLK_GATE_REG_OFFSET_SATA (19) 297#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) 298#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) 299#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) 300#define PM_CLK_GATE_REG_OFFSET_TIMER (14) 301#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) 302#define PM_CLK_GATE_REG_OFFSET_HCIE (12) 303#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) 304#define PM_CLK_GATE_REG_OFFSET_GPIO (10) 305#define PM_CLK_GATE_REG_OFFSET_UART3 (9) 306#define PM_CLK_GATE_REG_OFFSET_UART2 (8) 307#define PM_CLK_GATE_REG_OFFSET_UART1 (7) 308#define PM_CLK_GATE_REG_OFFSET_RTC (5) 309#define PM_CLK_GATE_REG_OFFSET_GDMA (4) 310#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) 311#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) 312#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) 313 314/* PM_SOFT_RST_REG */ 315#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) 316#define PM_SOFT_RST_REG_OFFST_CPU1 (29) 317#define PM_SOFT_RST_REG_OFFST_CPU0 (28) 318#define PM_SOFT_RST_REG_OFFST_SDIO (25) 319#define PM_SOFT_RST_REG_OFFST_GPU (24) 320#define PM_SOFT_RST_REG_OFFST_CIM (23) 321#define PM_SOFT_RST_REG_OFFST_LCDC (22) 322#define PM_SOFT_RST_REG_OFFST_I2S (21) 323#define PM_SOFT_RST_REG_OFFST_RAID (20) 324#define PM_SOFT_RST_REG_OFFST_SATA (19) 325#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) 326#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) 327#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) 328#define PM_SOFT_RST_REG_OFFST_TIMER (14) 329#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) 330#define PM_SOFT_RST_REG_OFFST_HCIE (12) 331#define PM_SOFT_RST_REG_OFFST_SWITCH (11) 332#define PM_SOFT_RST_REG_OFFST_GPIO (10) 333#define PM_SOFT_RST_REG_OFFST_UART3 (9) 334#define PM_SOFT_RST_REG_OFFST_UART2 (8) 335#define PM_SOFT_RST_REG_OFFST_UART1 (7) 336#define PM_SOFT_RST_REG_OFFST_RTC (5) 337#define PM_SOFT_RST_REG_OFFST_GDMA (4) 338#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) 339#define PM_SOFT_RST_REG_OFFST_DMC (2) 340#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) 341#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) 342#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) 343 344/* PMHS_CFG_REG */ 345#define PM_HS_CFG_REG_OFFSET_SDIO (25) 346#define PM_HS_CFG_REG_OFFSET_GPU (24) 347#define PM_HS_CFG_REG_OFFSET_CIM (23) 348#define PM_HS_CFG_REG_OFFSET_LCDC (22) 349#define PM_HS_CFG_REG_OFFSET_I2S (21) 350#define PM_HS_CFG_REG_OFFSET_RAID (20) 351#define PM_HS_CFG_REG_OFFSET_SATA (19) 352#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) 353#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) 354#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) 355#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) 356#define PM_HS_CFG_REG_OFFSET_TIMER (14) 357#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) 358#define PM_HS_CFG_REG_OFFSET_HCIE (12) 359#define PM_HS_CFG_REG_OFFSET_SWITCH (11) 360#define PM_HS_CFG_REG_OFFSET_GPIO (10) 361#define PM_HS_CFG_REG_OFFSET_UART3 (9) 362#define PM_HS_CFG_REG_OFFSET_UART2 (8) 363#define PM_HS_CFG_REG_OFFSET_UART1 (7) 364#define PM_HS_CFG_REG_OFFSET_RTC (5) 365#define PM_HS_CFG_REG_OFFSET_GDMA (4) 366#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) 367#define PM_HS_CFG_REG_OFFSET_DMC (2) 368#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) 369#define PM_HS_CFG_REG_MASK (0x03FFFFBE) 370#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) 371 372/* PM_CACTIVE_STA_REG */ 373#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) 374#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) 375#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) 376#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) 377#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) 378#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) 379#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) 380#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) 381#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) 382#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) 383#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) 384#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) 385#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) 386#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) 387#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) 388#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) 389#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) 390#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) 391#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) 392#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) 393#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) 394#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) 395#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) 396#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) 397#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) 398 399/* PM_PWR_STA_REG */ 400#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) 401#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) 402#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) 403#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) 404#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) 405#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) 406#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) 407#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) 408#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) 409#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) 410#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) 411#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) 412#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) 413#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) 414#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) 415#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) 416#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) 417#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) 418#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) 419#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) 420#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) 421#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) 422#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) 423#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) 424#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) 425 426/* PM_CLK_CTRL_REG */ 427#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) 428#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) 429#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) 430#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) 431#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) 432#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) 433#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) 434#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) 435#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) 436#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) 437#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) 438#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) 439#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) 440#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) 441#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) 442#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) 443 444#define PM_CPU_CLK_DIV(DIV) { \ 445 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ 446 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ 447} 448 449#define PM_PLL_CPU_SEL(CPU) { \ 450 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ 451 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ 452} 453 454/* PM_PLL_LCD_I2S_CTRL_REG */ 455#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) 456#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) 457#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) 458#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) 459#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) 460 461/* PM_PLL_HM_PD_CTRL_REG */ 462#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) 463#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) 464#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) 465#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) 466#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) 467#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) 468#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) 469#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) 470 471/* PM_WDT_CTRL_REG */ 472#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) 473 474/* PM_CSR_REG - Clock Scaling Register*/ 475#define PM_CSR_REG_OFFSET_CSR_EN (30) 476#define PM_CSR_REG_OFFSET_CSR_NUM (0) 477 478#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK) 479 480/* Software reset*/ 481#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK) 482 483/* 484 * CNS3XXX support several power saving mode as following, 485 * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate 486 */ 487#define CNS3XXX_PWR_CPU_MODE_DFS (0) 488#define CNS3XXX_PWR_CPU_MODE_IDLE (1) 489#define CNS3XXX_PWR_CPU_MODE_HALT (2) 490#define CNS3XXX_PWR_CPU_MODE_DOZE (3) 491#define CNS3XXX_PWR_CPU_MODE_SLEEP (4) 492#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5) 493 494#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK) 495#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK 496 497/* Change CPU frequency and divider */ 498#define CNS3XXX_PWR_PLL_CPU_300MHZ (0) 499#define CNS3XXX_PWR_PLL_CPU_333MHZ (1) 500#define CNS3XXX_PWR_PLL_CPU_366MHZ (2) 501#define CNS3XXX_PWR_PLL_CPU_400MHZ (3) 502#define CNS3XXX_PWR_PLL_CPU_433MHZ (4) 503#define CNS3XXX_PWR_PLL_CPU_466MHZ (5) 504#define CNS3XXX_PWR_PLL_CPU_500MHZ (6) 505#define CNS3XXX_PWR_PLL_CPU_533MHZ (7) 506#define CNS3XXX_PWR_PLL_CPU_566MHZ (8) 507#define CNS3XXX_PWR_PLL_CPU_600MHZ (9) 508#define CNS3XXX_PWR_PLL_CPU_633MHZ (10) 509#define CNS3XXX_PWR_PLL_CPU_666MHZ (11) 510#define CNS3XXX_PWR_PLL_CPU_700MHZ (12) 511 512#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0) 513#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1) 514#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2) 515 516/* Change DDR2 frequency */ 517#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0) 518#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1) 519#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2) 520#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3) 521 522void cns3xxx_pwr_soft_rst(unsigned int block); 523void cns3xxx_pwr_clk_en(unsigned int block); 524int cns3xxx_cpu_clock(void); 525 526/* 527 * ARM11 MPCore interrupt sources (primary GIC) 528 */ 529#define IRQ_TC11MP_GIC_START 32 530 531#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0) 532#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1) 533#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2) 534#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3) 535#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4) 536#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5) 537#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6) 538#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7) 539#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8) 540#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9) 541#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10) 542#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11) 543#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12) 544#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13) 545#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14) 546#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15) 547#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16) 548 549#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17) 550#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18) 551#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19) 552#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20) 553#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21) 554#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22) 555#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23) 556#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24) 557#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25) 558#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26) 559 560#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27) 561#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28) 562#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29) 563#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30) 564#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31) 565#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32) 566#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33) 567#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34) 568#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35) 569 570#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36) 571#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37) 572#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38) 573#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39) 574#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40) 575#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41) 576#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42) 577#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43) 578#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44) 579#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45) 580#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46) 581#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47) 582#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48) 583#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49) 584#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50) 585#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51) 586#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52) 587#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53) 588#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54) 589 590#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55) 591#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56) 592#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57) 593#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58) 594#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59) 595#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60) 596#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61) 597#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62) 598#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63) 599 600#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64) 601 602#endif /* __MACH_BOARD_CNS3XXX_H */ 603