1/*
2 * TI DaVinci DM646X EVM board
3 *
4 * Derived from: arch/arm/mach-davinci/board-evm.c
5 * Copyright (C) 2006 Texas Instruments.
6 *
7 * (C) 2007-2008, MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 *
13 */
14
15/**************************************************************************
16 * Included Files
17 **************************************************************************/
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/leds.h>
22#include <linux/gpio.h>
23#include <linux/platform_device.h>
24#include <linux/i2c.h>
25#include <linux/platform_data/at24.h>
26#include <linux/i2c/pcf857x.h>
27
28#include <media/tvp514x.h>
29#include <media/adv7343.h>
30
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/partitions.h>
34#include <linux/clk.h>
35#include <linux/export.h>
36#include <linux/platform_data/gpio-davinci.h>
37#include <linux/platform_data/i2c-davinci.h>
38#include <linux/platform_data/mtd-davinci.h>
39#include <linux/platform_data/mtd-davinci-aemif.h>
40
41#include <asm/mach-types.h>
42#include <asm/mach/arch.h>
43
44#include <mach/common.h>
45#include <mach/irqs.h>
46#include <mach/serial.h>
47#include <mach/clock.h>
48#include <mach/cdce949.h>
49
50#include "davinci.h"
51#include "clock.h"
52
53#define NAND_BLOCK_SIZE		SZ_128K
54
55/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
56 * and U-Boot environment this avoids dependency on any particular combination
57 * of UBL, U-Boot or flashing tools etc.
58 */
59static struct mtd_partition davinci_nand_partitions[] = {
60	{
61		/* UBL, U-Boot with environment */
62		.name		= "bootloader",
63		.offset		= MTDPART_OFS_APPEND,
64		.size		= 16 * NAND_BLOCK_SIZE,
65		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
66	}, {
67		.name		= "kernel",
68		.offset		= MTDPART_OFS_APPEND,
69		.size		= SZ_4M,
70		.mask_flags	= 0,
71	}, {
72		.name		= "filesystem",
73		.offset		= MTDPART_OFS_APPEND,
74		.size		= MTDPART_SIZ_FULL,
75		.mask_flags	= 0,
76	}
77};
78
79static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
80	.wsetup		= 29,
81	.wstrobe	= 24,
82	.whold		= 14,
83	.rsetup		= 19,
84	.rstrobe	= 33,
85	.rhold		= 0,
86	.ta		= 29,
87};
88
89static struct davinci_nand_pdata davinci_nand_data = {
90	.mask_cle 		= 0x80000,
91	.mask_ale 		= 0x40000,
92	.parts			= davinci_nand_partitions,
93	.nr_parts		= ARRAY_SIZE(davinci_nand_partitions),
94	.ecc_mode		= NAND_ECC_HW,
95	.ecc_bits		= 1,
96	.options		= 0,
97};
98
99static struct resource davinci_nand_resources[] = {
100	{
101		.start		= DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
102		.end		= DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
103		.flags		= IORESOURCE_MEM,
104	}, {
105		.start		= DM646X_ASYNC_EMIF_CONTROL_BASE,
106		.end		= DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
107		.flags		= IORESOURCE_MEM,
108	},
109};
110
111static struct platform_device davinci_nand_device = {
112	.name			= "davinci_nand",
113	.id			= 0,
114
115	.num_resources		= ARRAY_SIZE(davinci_nand_resources),
116	.resource		= davinci_nand_resources,
117
118	.dev			= {
119		.platform_data	= &davinci_nand_data,
120	},
121};
122
123#define HAS_ATA		IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
124
125/* CPLD Register 0 bits to control ATA */
126#define DM646X_EVM_ATA_RST		BIT(0)
127#define DM646X_EVM_ATA_PWD		BIT(1)
128
129/* CPLD Register 0 Client: used for I/O Control */
130static int cpld_reg0_probe(struct i2c_client *client,
131			   const struct i2c_device_id *id)
132{
133	if (HAS_ATA) {
134		u8 data;
135		struct i2c_msg msg[2] = {
136			{
137				.addr = client->addr,
138				.flags = I2C_M_RD,
139				.len = 1,
140				.buf = &data,
141			},
142			{
143				.addr = client->addr,
144				.flags = 0,
145				.len = 1,
146				.buf = &data,
147			},
148		};
149
150		/* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
151		i2c_transfer(client->adapter, msg, 1);
152		data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
153		i2c_transfer(client->adapter, msg + 1, 1);
154	}
155
156	return 0;
157}
158
159static const struct i2c_device_id cpld_reg_ids[] = {
160	{ "cpld_reg0", 0, },
161	{ },
162};
163
164static struct i2c_driver dm6467evm_cpld_driver = {
165	.driver.name	= "cpld_reg0",
166	.id_table	= cpld_reg_ids,
167	.probe		= cpld_reg0_probe,
168};
169
170/* LEDS */
171
172static struct gpio_led evm_leds[] = {
173	{ .name = "DS1", .active_low = 1, },
174	{ .name = "DS2", .active_low = 1, },
175	{ .name = "DS3", .active_low = 1, },
176	{ .name = "DS4", .active_low = 1, },
177};
178
179static const struct gpio_led_platform_data evm_led_data = {
180	.num_leds = ARRAY_SIZE(evm_leds),
181	.leds     = evm_leds,
182};
183
184static struct platform_device *evm_led_dev;
185
186static int evm_led_setup(struct i2c_client *client, int gpio,
187			unsigned int ngpio, void *c)
188{
189	struct gpio_led *leds = evm_leds;
190	int status;
191
192	while (ngpio--) {
193		leds->gpio = gpio++;
194		leds++;
195	}
196
197	evm_led_dev = platform_device_alloc("leds-gpio", 0);
198	platform_device_add_data(evm_led_dev, &evm_led_data,
199				sizeof(evm_led_data));
200
201	evm_led_dev->dev.parent = &client->dev;
202	status = platform_device_add(evm_led_dev);
203	if (status < 0) {
204		platform_device_put(evm_led_dev);
205		evm_led_dev = NULL;
206	}
207	return status;
208}
209
210static int evm_led_teardown(struct i2c_client *client, int gpio,
211				unsigned ngpio, void *c)
212{
213	if (evm_led_dev) {
214		platform_device_unregister(evm_led_dev);
215		evm_led_dev = NULL;
216	}
217	return 0;
218}
219
220static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
221
222static int evm_sw_setup(struct i2c_client *client, int gpio,
223			unsigned ngpio, void *c)
224{
225	int status;
226	int i;
227	char label[10];
228
229	for (i = 0; i < 4; ++i) {
230		snprintf(label, 10, "user_sw%d", i);
231		status = gpio_request(gpio, label);
232		if (status)
233			goto out_free;
234		evm_sw_gpio[i] = gpio++;
235
236		status = gpio_direction_input(evm_sw_gpio[i]);
237		if (status) {
238			gpio_free(evm_sw_gpio[i]);
239			evm_sw_gpio[i] = -EINVAL;
240			goto out_free;
241		}
242
243		status = gpio_export(evm_sw_gpio[i], 0);
244		if (status) {
245			gpio_free(evm_sw_gpio[i]);
246			evm_sw_gpio[i] = -EINVAL;
247			goto out_free;
248		}
249	}
250	return status;
251out_free:
252	for (i = 0; i < 4; ++i) {
253		if (evm_sw_gpio[i] != -EINVAL) {
254			gpio_free(evm_sw_gpio[i]);
255			evm_sw_gpio[i] = -EINVAL;
256		}
257	}
258	return status;
259}
260
261static int evm_sw_teardown(struct i2c_client *client, int gpio,
262			unsigned ngpio, void *c)
263{
264	int i;
265
266	for (i = 0; i < 4; ++i) {
267		if (evm_sw_gpio[i] != -EINVAL) {
268			gpio_unexport(evm_sw_gpio[i]);
269			gpio_free(evm_sw_gpio[i]);
270			evm_sw_gpio[i] = -EINVAL;
271		}
272	}
273	return 0;
274}
275
276static int evm_pcf_setup(struct i2c_client *client, int gpio,
277			unsigned int ngpio, void *c)
278{
279	int status;
280
281	if (ngpio < 8)
282		return -EINVAL;
283
284	status = evm_sw_setup(client, gpio, 4, c);
285	if (status)
286		return status;
287
288	return evm_led_setup(client, gpio+4, 4, c);
289}
290
291static int evm_pcf_teardown(struct i2c_client *client, int gpio,
292			unsigned int ngpio, void *c)
293{
294	BUG_ON(ngpio < 8);
295
296	evm_sw_teardown(client, gpio, 4, c);
297	evm_led_teardown(client, gpio+4, 4, c);
298
299	return 0;
300}
301
302static struct pcf857x_platform_data pcf_data = {
303	.gpio_base	= DAVINCI_N_GPIO+1,
304	.setup		= evm_pcf_setup,
305	.teardown	= evm_pcf_teardown,
306};
307
308/* Most of this EEPROM is unused, but U-Boot uses some data:
309 *  - 0x7f00, 6 bytes Ethernet Address
310 *  - ... newer boards may have more
311 */
312
313static struct at24_platform_data eeprom_info = {
314	.byte_len       = (256*1024) / 8,
315	.page_size      = 64,
316	.flags          = AT24_FLAG_ADDR16,
317	.setup          = davinci_get_mac_addr,
318	.context	= (void *)0x7f00,
319};
320
321static u8 dm646x_iis_serializer_direction[] = {
322       TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
323};
324
325static u8 dm646x_dit_serializer_direction[] = {
326       TX_MODE,
327};
328
329static struct snd_platform_data dm646x_evm_snd_data[] = {
330	{
331		.tx_dma_offset  = 0x400,
332		.rx_dma_offset  = 0x400,
333		.op_mode        = DAVINCI_MCASP_IIS_MODE,
334		.num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
335		.tdm_slots      = 2,
336		.serial_dir     = dm646x_iis_serializer_direction,
337		.asp_chan_q     = EVENTQ_0,
338	},
339	{
340		.tx_dma_offset  = 0x400,
341		.rx_dma_offset  = 0,
342		.op_mode        = DAVINCI_MCASP_DIT_MODE,
343		.num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
344		.tdm_slots      = 32,
345		.serial_dir     = dm646x_dit_serializer_direction,
346		.asp_chan_q     = EVENTQ_0,
347	},
348};
349
350static struct i2c_client *cpld_client;
351
352static int cpld_video_probe(struct i2c_client *client,
353			const struct i2c_device_id *id)
354{
355	cpld_client = client;
356	return 0;
357}
358
359static int cpld_video_remove(struct i2c_client *client)
360{
361	cpld_client = NULL;
362	return 0;
363}
364
365static const struct i2c_device_id cpld_video_id[] = {
366	{ "cpld_video", 0 },
367	{ }
368};
369
370static struct i2c_driver cpld_video_driver = {
371	.driver = {
372		.name	= "cpld_video",
373	},
374	.probe		= cpld_video_probe,
375	.remove		= cpld_video_remove,
376	.id_table	= cpld_video_id,
377};
378
379static void evm_init_cpld(void)
380{
381	i2c_add_driver(&cpld_video_driver);
382}
383
384static struct i2c_board_info __initdata i2c_info[] =  {
385	{
386		I2C_BOARD_INFO("24c256", 0x50),
387		.platform_data  = &eeprom_info,
388	},
389	{
390		I2C_BOARD_INFO("pcf8574a", 0x38),
391		.platform_data	= &pcf_data,
392	},
393	{
394		I2C_BOARD_INFO("cpld_reg0", 0x3a),
395	},
396	{
397		I2C_BOARD_INFO("tlv320aic33", 0x18),
398	},
399	{
400		I2C_BOARD_INFO("cpld_video", 0x3b),
401	},
402	{
403		I2C_BOARD_INFO("cdce949", 0x6c),
404	},
405};
406
407static struct davinci_i2c_platform_data i2c_pdata = {
408	.bus_freq       = 100 /* kHz */,
409	.bus_delay      = 0 /* usec */,
410};
411
412#define VCH2CLK_MASK		(BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
413#define VCH2CLK_SYSCLK8		(BIT(9))
414#define VCH2CLK_AUXCLK		(BIT(9) | BIT(8))
415#define VCH3CLK_MASK		(BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
416#define VCH3CLK_SYSCLK8		(BIT(13))
417#define VCH3CLK_AUXCLK		(BIT(14) | BIT(13))
418
419#define VIDCH2CLK		(BIT(10))
420#define VIDCH3CLK		(BIT(11))
421#define VIDCH1CLK		(BIT(4))
422#define TVP7002_INPUT		(BIT(4))
423#define TVP5147_INPUT		(~BIT(4))
424#define VPIF_INPUT_ONE_CHANNEL	(BIT(5))
425#define VPIF_INPUT_TWO_CHANNEL	(~BIT(5))
426#define TVP5147_CH0		"tvp514x-0"
427#define TVP5147_CH1		"tvp514x-1"
428
429/* spin lock for updating above registers */
430static spinlock_t vpif_reg_lock;
431
432static int set_vpif_clock(int mux_mode, int hd)
433{
434	unsigned long flags;
435	unsigned int value;
436	int val = 0;
437	int err = 0;
438
439	if (!cpld_client)
440		return -ENXIO;
441
442	/* disable the clock */
443	spin_lock_irqsave(&vpif_reg_lock, flags);
444	value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
445	value |= (VIDCH3CLK | VIDCH2CLK);
446	__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
447	spin_unlock_irqrestore(&vpif_reg_lock, flags);
448
449	val = i2c_smbus_read_byte(cpld_client);
450	if (val < 0)
451		return val;
452
453	if (mux_mode == 1)
454		val &= ~0x40;
455	else
456		val |= 0x40;
457
458	err = i2c_smbus_write_byte(cpld_client, val);
459	if (err)
460		return err;
461
462	value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
463	value &= ~(VCH2CLK_MASK);
464	value &= ~(VCH3CLK_MASK);
465
466	if (hd >= 1)
467		value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
468	else
469		value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
470
471	__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
472
473	spin_lock_irqsave(&vpif_reg_lock, flags);
474	value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
475	/* enable the clock */
476	value &= ~(VIDCH3CLK | VIDCH2CLK);
477	__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
478	spin_unlock_irqrestore(&vpif_reg_lock, flags);
479
480	return 0;
481}
482
483static struct vpif_subdev_info dm646x_vpif_subdev[] = {
484	{
485		.name	= "adv7343",
486		.board_info = {
487			I2C_BOARD_INFO("adv7343", 0x2a),
488		},
489	},
490	{
491		.name	= "ths7303",
492		.board_info = {
493			I2C_BOARD_INFO("ths7303", 0x2c),
494		},
495	},
496};
497
498static const struct vpif_output dm6467_ch0_outputs[] = {
499	{
500		.output = {
501			.index = 0,
502			.name = "Composite",
503			.type = V4L2_OUTPUT_TYPE_ANALOG,
504			.capabilities = V4L2_OUT_CAP_STD,
505			.std = V4L2_STD_ALL,
506		},
507		.subdev_name = "adv7343",
508		.output_route = ADV7343_COMPOSITE_ID,
509	},
510	{
511		.output = {
512			.index = 1,
513			.name = "Component",
514			.type = V4L2_OUTPUT_TYPE_ANALOG,
515			.capabilities = V4L2_OUT_CAP_DV_TIMINGS,
516		},
517		.subdev_name = "adv7343",
518		.output_route = ADV7343_COMPONENT_ID,
519	},
520	{
521		.output = {
522			.index = 2,
523			.name = "S-Video",
524			.type = V4L2_OUTPUT_TYPE_ANALOG,
525			.capabilities = V4L2_OUT_CAP_STD,
526			.std = V4L2_STD_ALL,
527		},
528		.subdev_name = "adv7343",
529		.output_route = ADV7343_SVIDEO_ID,
530	},
531};
532
533static struct vpif_display_config dm646x_vpif_display_config = {
534	.set_clock	= set_vpif_clock,
535	.subdevinfo	= dm646x_vpif_subdev,
536	.subdev_count	= ARRAY_SIZE(dm646x_vpif_subdev),
537	.chan_config[0] = {
538		.outputs = dm6467_ch0_outputs,
539		.output_count = ARRAY_SIZE(dm6467_ch0_outputs),
540	},
541	.card_name	= "DM646x EVM",
542};
543
544/**
545 * setup_vpif_input_path()
546 * @channel: channel id (0 - CH0, 1 - CH1)
547 * @sub_dev_name: ptr sub device name
548 *
549 * This will set vpif input to capture data from tvp514x or
550 * tvp7002.
551 */
552static int setup_vpif_input_path(int channel, const char *sub_dev_name)
553{
554	int err = 0;
555	int val;
556
557	/* for channel 1, we don't do anything */
558	if (channel != 0)
559		return 0;
560
561	if (!cpld_client)
562		return -ENXIO;
563
564	val = i2c_smbus_read_byte(cpld_client);
565	if (val < 0)
566		return val;
567
568	if (!strcmp(sub_dev_name, TVP5147_CH0) ||
569	    !strcmp(sub_dev_name, TVP5147_CH1))
570		val &= TVP5147_INPUT;
571	else
572		val |= TVP7002_INPUT;
573
574	err = i2c_smbus_write_byte(cpld_client, val);
575	if (err)
576		return err;
577	return 0;
578}
579
580/**
581 * setup_vpif_input_channel_mode()
582 * @mux_mode:  mux mode. 0 - 1 channel or (1) - 2 channel
583 *
584 * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
585 */
586static int setup_vpif_input_channel_mode(int mux_mode)
587{
588	unsigned long flags;
589	int err = 0;
590	int val;
591	u32 value;
592
593	if (!cpld_client)
594		return -ENXIO;
595
596	val = i2c_smbus_read_byte(cpld_client);
597	if (val < 0)
598		return val;
599
600	spin_lock_irqsave(&vpif_reg_lock, flags);
601	value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
602	if (mux_mode) {
603		val &= VPIF_INPUT_TWO_CHANNEL;
604		value |= VIDCH1CLK;
605	} else {
606		val |= VPIF_INPUT_ONE_CHANNEL;
607		value &= ~VIDCH1CLK;
608	}
609	__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
610	spin_unlock_irqrestore(&vpif_reg_lock, flags);
611
612	err = i2c_smbus_write_byte(cpld_client, val);
613	if (err)
614		return err;
615
616	return 0;
617}
618
619static struct tvp514x_platform_data tvp5146_pdata = {
620	.clk_polarity = 0,
621	.hs_polarity = 1,
622	.vs_polarity = 1
623};
624
625#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
626
627static struct vpif_subdev_info vpif_capture_sdev_info[] = {
628	{
629		.name	= TVP5147_CH0,
630		.board_info = {
631			I2C_BOARD_INFO("tvp5146", 0x5d),
632			.platform_data = &tvp5146_pdata,
633		},
634	},
635	{
636		.name	= TVP5147_CH1,
637		.board_info = {
638			I2C_BOARD_INFO("tvp5146", 0x5c),
639			.platform_data = &tvp5146_pdata,
640		},
641	},
642};
643
644static const struct vpif_input dm6467_ch0_inputs[] = {
645	{
646		.input = {
647			.index = 0,
648			.name = "Composite",
649			.type = V4L2_INPUT_TYPE_CAMERA,
650			.capabilities = V4L2_IN_CAP_STD,
651			.std = TVP514X_STD_ALL,
652		},
653		.subdev_name = TVP5147_CH0,
654		.input_route = INPUT_CVBS_VI2B,
655		.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
656	},
657};
658
659static const struct vpif_input dm6467_ch1_inputs[] = {
660       {
661		.input = {
662			.index = 0,
663			.name = "S-Video",
664			.type = V4L2_INPUT_TYPE_CAMERA,
665			.capabilities = V4L2_IN_CAP_STD,
666			.std = TVP514X_STD_ALL,
667		},
668		.subdev_name = TVP5147_CH1,
669		.input_route = INPUT_SVIDEO_VI2C_VI1C,
670		.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
671	},
672};
673
674static struct vpif_capture_config dm646x_vpif_capture_cfg = {
675	.setup_input_path = setup_vpif_input_path,
676	.setup_input_channel_mode = setup_vpif_input_channel_mode,
677	.subdev_info = vpif_capture_sdev_info,
678	.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
679	.chan_config[0] = {
680		.inputs = dm6467_ch0_inputs,
681		.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
682		.vpif_if = {
683			.if_type = VPIF_IF_BT656,
684			.hd_pol = 1,
685			.vd_pol = 1,
686			.fid_pol = 0,
687		},
688	},
689	.chan_config[1] = {
690		.inputs = dm6467_ch1_inputs,
691		.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
692		.vpif_if = {
693			.if_type = VPIF_IF_BT656,
694			.hd_pol = 1,
695			.vd_pol = 1,
696			.fid_pol = 0,
697		},
698	},
699};
700
701static void __init evm_init_video(void)
702{
703	spin_lock_init(&vpif_reg_lock);
704
705	dm646x_setup_vpif(&dm646x_vpif_display_config,
706			  &dm646x_vpif_capture_cfg);
707}
708
709static void __init evm_init_i2c(void)
710{
711	davinci_init_i2c(&i2c_pdata);
712	i2c_add_driver(&dm6467evm_cpld_driver);
713	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
714	evm_init_cpld();
715	evm_init_video();
716}
717
718#define CDCE949_XIN_RATE	27000000
719
720/* CDCE949 support - "lpsc" field is overridden to work as clock number */
721static struct clk cdce_clk_in = {
722	.name	= "cdce_xin",
723	.rate	= CDCE949_XIN_RATE,
724};
725
726static struct clk_lookup cdce_clks[] = {
727	CLK(NULL, "xin", &cdce_clk_in),
728	CLK(NULL, NULL, NULL),
729};
730
731static void __init cdce_clk_init(void)
732{
733	struct clk_lookup *c;
734	struct clk *clk;
735
736	for (c = cdce_clks; c->clk; c++) {
737		clk = c->clk;
738		clkdev_add(c);
739		clk_register(clk);
740	}
741}
742
743#define DM6467T_EVM_REF_FREQ		33000000
744
745static void __init davinci_map_io(void)
746{
747	dm646x_init();
748
749	if (machine_is_davinci_dm6467tevm())
750		davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
751
752	cdce_clk_init();
753}
754
755#define DM646X_EVM_PHY_ID		"davinci_mdio-0:01"
756/*
757 * The following EDMA channels/slots are not being used by drivers (for
758 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
759 * reserved for codecs on the DSP side.
760 */
761static const s16 dm646x_dma_rsv_chans[][2] = {
762	/* (offset, number) */
763	{ 0,  4},
764	{13,  3},
765	{24,  4},
766	{30,  2},
767	{54,  3},
768	{-1, -1}
769};
770
771static const s16 dm646x_dma_rsv_slots[][2] = {
772	/* (offset, number) */
773	{ 0,  4},
774	{13,  3},
775	{24,  4},
776	{30,  2},
777	{54,  3},
778	{128, 384},
779	{-1, -1}
780};
781
782static struct edma_rsv_info dm646x_edma_rsv[] = {
783	{
784		.rsv_chans	= dm646x_dma_rsv_chans,
785		.rsv_slots	= dm646x_dma_rsv_slots,
786	},
787};
788
789static __init void evm_init(void)
790{
791	int ret;
792	struct davinci_soc_info *soc_info = &davinci_soc_info;
793
794	ret = dm646x_gpio_register();
795	if (ret)
796		pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
797
798	evm_init_i2c();
799	davinci_serial_init(dm646x_serial_device);
800	dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
801	dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
802
803	if (machine_is_davinci_dm6467tevm())
804		davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
805
806	platform_device_register(&davinci_nand_device);
807
808	if (davinci_aemif_setup(&davinci_nand_device))
809		pr_warn("%s: Cannot configure AEMIF.\n", __func__);
810
811	dm646x_init_edma(dm646x_edma_rsv);
812
813	if (HAS_ATA)
814		davinci_init_ide();
815
816	soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
817}
818
819MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
820	.atag_offset  = 0x100,
821	.map_io       = davinci_map_io,
822	.init_irq     = davinci_irq_init,
823	.init_time	= davinci_timer_init,
824	.init_machine = evm_init,
825	.init_late	= davinci_init_late,
826	.dma_zone_size	= SZ_128M,
827	.restart	= davinci_restart,
828MACHINE_END
829
830MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
831	.atag_offset  = 0x100,
832	.map_io       = davinci_map_io,
833	.init_irq     = davinci_irq_init,
834	.init_time	= davinci_timer_init,
835	.init_machine = evm_init,
836	.init_late	= davinci_init_late,
837	.dma_zone_size	= SZ_128M,
838	.restart	= davinci_restart,
839MACHINE_END
840
841