omap4-common.c revision b6a4226c14001b0aa20b11c69190cb89d2237d3d 
1/*
2 * OMAP4 specific common source file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Author:
6 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 *
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/memblock.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/export.h>
22
23#include <asm/hardware/gic.h>
24#include <asm/hardware/cache-l2x0.h>
25#include <asm/mach/map.h>
26#include <asm/memblock.h>
27
28#include "../plat-omap/sram.h"
29
30#include "omap-wakeupgen.h"
31#include "soc.h"
32#include "iomap.h"
33#include "common.h"
34#include "mmc.h"
35#include "hsmmc.h"
36#include "omap4-sar-layout.h"
37#include "omap-secure.h"
38
39#ifdef CONFIG_CACHE_L2X0
40static void __iomem *l2cache_base;
41#endif
42
43static void __iomem *sar_ram_base;
44
45#ifdef CONFIG_OMAP4_ERRATA_I688
46/* Used to implement memory barrier on DRAM path */
47#define OMAP4_DRAM_BARRIER_VA			0xfe600000
48
49void __iomem *dram_sync, *sram_sync;
50
51static phys_addr_t paddr;
52static u32 size;
53
54void omap_bus_sync(void)
55{
56	if (dram_sync && sram_sync) {
57		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
58		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
59		isb();
60	}
61}
62EXPORT_SYMBOL(omap_bus_sync);
63
64/* Steal one page physical memory for barrier implementation */
65int __init omap_barrier_reserve_memblock(void)
66{
67
68	size = ALIGN(PAGE_SIZE, SZ_1M);
69	paddr = arm_memblock_steal(size, SZ_1M);
70
71	return 0;
72}
73
74void __init omap_barriers_init(void)
75{
76	struct map_desc dram_io_desc[1];
77
78	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
79	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
80	dram_io_desc[0].length = size;
81	dram_io_desc[0].type = MT_MEMORY_SO;
82	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
83	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
84	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
85
86	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
87		(long long) paddr, dram_io_desc[0].virtual);
88
89}
90#else
91void __init omap_barriers_init(void)
92{}
93#endif
94
95void __init gic_init_irq(void)
96{
97	void __iomem *omap_irq_base;
98	void __iomem *gic_dist_base_addr;
99
100	/* Static mapping, never released */
101	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
102	BUG_ON(!gic_dist_base_addr);
103
104	/* Static mapping, never released */
105	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
106	BUG_ON(!omap_irq_base);
107
108	omap_wakeupgen_init();
109
110	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
111}
112
113#ifdef CONFIG_CACHE_L2X0
114
115void __iomem *omap4_get_l2cache_base(void)
116{
117	return l2cache_base;
118}
119
120static void omap4_l2x0_disable(void)
121{
122	/* Disable PL310 L2 Cache controller */
123	omap_smc1(0x102, 0x0);
124}
125
126static void omap4_l2x0_set_debug(unsigned long val)
127{
128	/* Program PL310 L2 Cache controller debug register */
129	omap_smc1(0x100, val);
130}
131
132static int __init omap_l2_cache_init(void)
133{
134	u32 aux_ctrl = 0;
135
136	/*
137	 * To avoid code running on other OMAPs in
138	 * multi-omap builds
139	 */
140	if (!cpu_is_omap44xx())
141		return -ENODEV;
142
143	/* Static mapping, never released */
144	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
145	if (WARN_ON(!l2cache_base))
146		return -ENOMEM;
147
148	/*
149	 * 16-way associativity, parity disabled
150	 * Way size - 32KB (es1.0)
151	 * Way size - 64KB (es2.0 +)
152	 */
153	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
154			(0x1 << 25) |
155			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
156			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
157
158	if (omap_rev() == OMAP4430_REV_ES1_0) {
159		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
160	} else {
161		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
162			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
163			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
164			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
165			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
166	}
167	if (omap_rev() != OMAP4430_REV_ES1_0)
168		omap_smc1(0x109, aux_ctrl);
169
170	/* Enable PL310 L2 Cache controller */
171	omap_smc1(0x102, 0x1);
172
173	if (of_have_populated_dt())
174		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
175	else
176		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
177
178	/*
179	 * Override default outer_cache.disable with a OMAP4
180	 * specific one
181	*/
182	outer_cache.disable = omap4_l2x0_disable;
183	outer_cache.set_debug = omap4_l2x0_set_debug;
184
185	return 0;
186}
187early_initcall(omap_l2_cache_init);
188#endif
189
190void __iomem *omap4_get_sar_ram_base(void)
191{
192	return sar_ram_base;
193}
194
195/*
196 * SAR RAM used to save and restore the HW
197 * context in low power modes
198 */
199static int __init omap4_sar_ram_init(void)
200{
201	/*
202	 * To avoid code running on other OMAPs in
203	 * multi-omap builds
204	 */
205	if (!cpu_is_omap44xx())
206		return -ENOMEM;
207
208	/* Static mapping, never released */
209	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
210	if (WARN_ON(!sar_ram_base))
211		return -ENOMEM;
212
213	return 0;
214}
215early_initcall(omap4_sar_ram_init);
216
217static struct of_device_id irq_match[] __initdata = {
218	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
219	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
220	{ }
221};
222
223void __init omap_gic_of_init(void)
224{
225	omap_wakeupgen_init();
226	of_irq_init(irq_match);
227}
228
229#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
230static int omap4_twl6030_hsmmc_late_init(struct device *dev)
231{
232	int irq = 0;
233	struct platform_device *pdev = container_of(dev,
234				struct platform_device, dev);
235	struct omap_mmc_platform_data *pdata = dev->platform_data;
236
237	/* Setting MMC1 Card detect Irq */
238	if (pdev->id == 0) {
239		irq = twl6030_mmc_card_detect_config();
240		if (irq < 0) {
241			dev_err(dev, "%s: Error card detect config(%d)\n",
242				__func__, irq);
243			return irq;
244		}
245		pdata->slots[0].card_detect_irq = irq;
246		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
247	}
248	return 0;
249}
250
251static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
252{
253	struct omap_mmc_platform_data *pdata;
254
255	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
256	if (!dev) {
257		pr_err("Failed %s\n", __func__);
258		return;
259	}
260	pdata = dev->platform_data;
261	pdata->init =	omap4_twl6030_hsmmc_late_init;
262}
263
264int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
265{
266	struct omap2_hsmmc_info *c;
267
268	omap_hsmmc_init(controllers);
269	for (c = controllers; c->mmc; c++) {
270		/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
271		if (!c->pdev)
272			continue;
273		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
274	}
275
276	return 0;
277}
278#else
279int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
280{
281	return 0;
282}
283#endif
284