| 1306c08a7cd7e6136490ab2bc728d2c39741003e |
|
10-Sep-2014 |
Rajendra Nayak <rnayak@ti.com> |
ARM: OMAP4+: Remove static iotable mappings for SRAM
In order to handle errata I688, a page of sram was reserved by doing a
static iotable map. Now that we use gen_pool to manage sram, we can
completely remove all of these static mappings and use gen_pool_alloc()
to get the one page of sram space needed to implement errata I688.
omap_bus_sync will be NOP until SRAM initialization happens.
Suggested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| ba394f0b6aa7a4a6afe67176da5d29f0ac59c48d |
|
14-Jul-2014 |
Sekhar Nori <nsekhar@ti.com> |
ARM: OMAP2+: l2c: squelch warning dump on power control setting
On OMAP SOCs using PL310 controllers, power_ctrl register is not
accessible from non-secure software even on PL310 versions which
support it. The secure code takes care of setting it up correctly
and power transitions are proven on these devices.
For example, AM437x has L2C-310 version r3p3 and ROM code on that
device does not support writing to L2C-310 power control register.
The L2C driver, however, tries writing to this register for all
revisions >= r3p0.
This leads to a warning dump on boot which leads most users to believe
that L2 cache is non-functional.
Since the problem is understood, and cannot be addressed through
software, replace the warning with a pr_info() while maintaining the
WARN_ON() for other truly unexpected scenarios.
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| b7196ab07890bb1bc8f364dc341ee1251919111b |
|
10-Jun-2014 |
Brian Norris <computersforpeace@gmail.com> |
ARM: OMAP2+: drop unused function
gic_init_irq() is no longer used as of:
commit b42b918194c4791510ac049e3d507169a7de8544
Author: Tony Lindgren <tony@atomide.com>
Date: Thu May 30 12:53:05 2013 -0700
ARM: OMAP2+: Remove board-omap4panda.c
Drop it.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| b39b14e62ac3d0a66d13123ef85aaa83fd7c90fc |
|
22-Apr-2014 |
Sekhar Nori <nsekhar@ti.com> |
ARM: l2c: omap2+: get rid of init call
Get rid of init call to initialize L2 cache. Instead use the init_early
machine hook. This helps in using the initialization routine across
SoCs without the need of ugly cpu_is_*() checks.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| d196483dfce233da7d6094371e694eadd7e4cc1b |
|
22-Apr-2014 |
Sekhar Nori <nsekhar@ti.com> |
ARM: l2c: omap2+: get rid of redundant cache replacement policy setting
L2 cache initialization for OMAP4 redundantly sets the cache policy to
Round-Robin. This is not needed since thats the PL310 default anyway.
Removing this reduces the number of platform specific aux control
settings.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 72ecbed1c5fe96ca5238c0c333fee3b5a858b6fb |
|
11-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: omap2: remove explicit non-secure access bits
Since we now always enable NS access to the unlock registers, this can
be removed from OMAP4. Remove the NS access bit for the interrupt
registers from OMAP4 as well - nothing in the kernel accesses that yet,
and we can add it in core code when we have the need.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| deb125abad130fc1200782048a79079f5a41af05 |
|
17-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: omap2: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 7eab0039d3ef35bddaf02bb87c9009d484d90eea |
|
17-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: omap2: remove explicit SMI calls to enable L2 cache
Now that OMAP2 uses the write_sec method, we don't need to enable the L2
cache in OMAP2 specific code; this can be done via the normal mechanisms
in the L2C code. Remove the OMAP2 specific code.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 36827edd2e3711749ff472949b9cf94f4cb700e9 |
|
16-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: omap2: implement new write_sec method
With the write_sec method, we no longer need to override the default
L2C disable method, and we no longer need the L2C set_debug method.
Both of these can be handled via the write_sec method.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 36bccb11a4ac7cc9d190c3062945f1c911a62801 |
|
19-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: remove platforms/SoCs setting early BRESP
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 1a5a954ce0dd8ba1fc8b5305bcdb6e4cf7d6939b |
|
16-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: fix register naming
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| cef3d92c5bd54b38ddca48c4394e0991be934385 |
|
19-Mar-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: omap2: remove ES1.0 support
Santosh says:
> But we should kill all of that since we long back decided to remove
> ES1.0 related code. The mach-omap code alreasy has removed the ES1.0
> compatibility so feel free to remove any specific ES1.0
> related stuff. That silicon is long dead.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| edfaf05c2fcb853fcf35f12aeb9c340f5913337f |
|
15-Apr-2014 |
Victor Kamensky <victor.kamensky@linaro.org> |
ARM: OMAP2+: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 5c61e61966076406a1ab238f5b8588a0caa26c16 |
|
03-Dec-2013 |
Sricharan R <r.sricharan@ti.com> |
ARM: DRA: Enable Crossbar IP support for DRA7XX
Enable the crossbar IP support for DRA7xx soc.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
|
| 74ed7bdcb41d32c7628c3bd1478b076e5b1ad8a4 |
|
22-Oct-2013 |
Strashko, Grygorii <grygorii.strashko@ti.com> |
ARM: OMAP4460: cpuidle: Extend PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD on cpuidle
The same workaround as ff999b8a0983ee15668394ed49e38d3568fc6859
"ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC ..."
need to be applied not only when system is booting, but when MPUSS hits
OSWR state through CPUIdle too. Without this WA the same issue is
reproduced now on boards PandaES and Tablet/Blaze with SOM OMAP4460
when CONFIG_CPU_IDLE is enabled.
After MPUSS has enterred OSWR and waken up:
- GIC distributor became disabled forever
- scheduling is not performed any more
Cc: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reported-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| b25f3e1c358434bf850220e04f28eebfc45eb634 |
|
10-Jan-2014 |
Taras Kondratiuk <taras.kondratiuk@linaro.org> |
ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
Kexec disables outer cache before jumping to reboot code, but it doesn't
flush it explicitly. Flush is done implicitly inside of l2x0_disable().
But some SoC's override default .disable handler and don't flush cache.
This may lead to a corrupted memory during Kexec reboot on these
platforms.
This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable()
handlers to make it consistent with default l2x0_disable().
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 2e2c9de207be043ee80161971c814d740759d3bc |
|
24-Oct-2013 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: add permission annotations to MT_MEMORY* mapping types
Document the permissions which the various MT_MEMORY* mapping types
will provide.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| b2ff4790612bbfa3433cc92e56445c2a40098e2c |
|
19-Nov-2013 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Remove legacy omap4_twl6030_hsmmc_init
This is no longer used, omap4 is device tree based now.
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 7b6d864b48d95e6ea1df7df64475b9cb9616dcf9 |
|
09-Jul-2013 |
Robin Holt <holt@sgi.com> |
reboot: arm: change reboot_mode to use enum reboot_mode
Preparing to move the parsing of reboot= to generic kernel code forces
the change in reboot_mode handling to use the enum.
[akpm@linux-foundation.org: fix arch/arm/mach-socfpga/socfpga.c]
Signed-off-by: Robin Holt <holt@sgi.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Russ Anderson <rja@sgi.com>
Cc: Robin Holt <holt@sgi.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
| ab4c2e1bbd316bd86b448fa0974ac66c0d2172b8 |
|
27-May-2013 |
Afzal Mohammed <afzal@ti.com> |
ARM: OMAP2+: separate out OMAP4 restart
Separate out OMAP4 restart and have it similar to other platforms, in
a different file. Main motive is to reuse omap4-common on platforms
other than OMAP4, like AM43x, even if OMAP4 is deselected (otherwise
would have caused build breakage).
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| fd1c07861491abf5e0e9ca06799bb5c48f99b64d |
|
25-Feb-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Fix the init code to have OMAP4460 errata available in DT build
OMAP4460 ROM code bug needs the GIC distributor and local timer
bases to be available for the bug work around. In current code, dt
case these bases are not initialized leading to failure of the
errata work-around.
Fix it by extracting the bases from dt blob and populating them.
Reported-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| da0e02a1e4a6348505cfe0cbb0d3a2717a2b5476 |
|
06-Feb-2013 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP5: Update SAR RAM base address
Update SAR RAM base address for OMAP5 based devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| 520f7bd73354f003a9a59937b28e4903d985c420 |
|
27-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.h
Now that we have GIC moved to drivers/irqchip and all GIC DT init for
platforms using irqchip_init, move gic.h and update the remaining
includes.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>
|
| 0529e315bbda5d502c93df2cfafba9bb337fbdf4 |
|
05-Nov-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: use common irqchip_init for GIC init
Convert all GIC DT initialization over to use common irqchip_init
function.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
|
| b76c8b19b082c3fc84725de0d3ba5ee1f571c0ae |
|
11-Jan-2013 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Use omap initcalls
This way the initcalls don't run on other SoCs on multiplatform
kernels. Otherwise we'll get something like this when booting
on vexpress:
omap_hwmod: _ensure_mpu_hwmod_is_setup: MPU initiator hwmod mpu not yet registered
...
WARNING: at arch/arm/mach-omap2/pm.c:82 _init_omap_device+0x74/0x94()
_init_omap_device: could not find omap_hwmod for mpu
...
omap-dma-engine omap-dma-engine: OMAP DMA engine driver
...
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| d9a16f9ab9332b7cf1c95086a4efb98a0d13a57a |
|
30-Oct-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: PRCM: split and relocate the PRM/CM globals setup
Split omap2_set_globals_prcm() into PRM, CM, and PRCM_MPU variants, since
these are all separate IP blocks. This should make it easier to move the
PRM, CM, PRCM_MPU code into drivers/ in future patchsets.
At this point arch/arm/plat-omap/include/plat/prcm.h is empty; a
subsequent patch will remove it, and remove the #include from all the
files that #include it.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
|
| 2f334a3896714b47e24cc4cd08eed11d1a7f0d8e |
|
30-Oct-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: PRCM: create SoC-specific chip restart functions
Split omap_prcm_restart() from mach-omap2/prcm.c into SoC-specific
variants. These functions need to be able to save the reboot reason
into the scratchpad RAM. This implies a dependency on both the PRM
and SCM IP blocks, so they've been moved into their own file. This
will eventually call functions in the PRM and SCM drivers, once those
are created.
Vaibhav Hiremath <hvaibhav@ti.com> identified an unused prototype in
the first version of this patch - now removed. Tony Lindgren
<tony@atomide.com> noted a compile problem with some RMK Kconfigs;
resolved in this patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
|
| b6a4226c14001b0aa20b11c69190cb89d2237d3d |
|
30-Oct-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: common: remove mach-omap2/common.c globals and map_common_io code
Get rid of the mach-omap2/common.c globals by moving the global
initialization for IP block addresses that must occur early into
mach-omap2/io.c. In the process, remove the *_map_common_io*() and
SoC-specific *set_globals* functions.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
|
| cd8ce159031813eb870a5f3d5b27c3be36cd6e3a |
|
17-Oct-2012 |
Colin Cross <ccross@android.com> |
ARM: OMAP4: retrigger localtimers after re-enabling gic
'Workaround for ROM bug because of CA9 r2pX gic control'
register change disables the gic distributor while the secondary
cpu is being booted. If a localtimer interrupt on the primary cpu
occurs when the distributor is turned off, the interrupt is lost,
and the localtimer never fires again.
Make the primary cpu wait for the secondary cpu to reenable the
gic distributor (with interrupts off for safety), and then
check if the pending bit is set in the localtimer but not the
gic. If so, ack it in the localtimer, and reset the timer with
the minimum timeout to trigger a new timer interrupt.
Signed-off-by: Colin Cross <ccross@android.com>
[s-jan@ti.com: adapted to k3.4 + validated functionality]
Signed-off-by: Sebastien Jan <s-jan@ti.com>
[t-kristo@ti.com: dropped generic ARM kernel exports from the code, rebased
to mainline]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| ff999b8a0983ee15668394ed49e38d3568fc6859 |
|
17-Oct-2012 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| bb77209432873214a796a70a4539e4ebdf3feb54 |
|
29-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Move omap2+ specific parts of sram.c to mach-omap2
Let's make the omap2+ specific parts private to mach-omap2.
This leaves just a minimal shared code into plat-omap like
it should be.
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| bf027ca13738b1548910351952c3fe9b63263a9a |
|
29-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Split sram.h to local headers and minimal shared header
Most of the defines are specific to omap1 and omap2+,
and should be in the local headers. Only minimal function
prototypes need to be shared.
As discussed on linux-arm-kernel, we want to avoid
relative includes for the arch/arm/*omap* shared code:
http://www.spinics.net/lists/linux-omap/msg80520.html
So this patch re-adds a minimal plat/sram.h.
The new plat/sram.h must not be included from drivers,
that will break build for omap2+ CONFIG_MULTIPLATFORM.
Note that this patch temporarily adds two more
relative includes; Those will be removed in the
following patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| f7a9b8a147cc10c7181cf0ca7b2b06cebf950140 |
|
01-Oct-2012 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: OMAP: Move plat/omap-secure.h locally to mach-omap2
Moving plat/omap-secure.h locally to mach-omap2/
as part of single zImage work
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 622297fdec22310d57cc3222a8fc337993c7cd23 |
|
02-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Make plat/sram.h local to plat-omap
We can move this from plat to be local to plat-omap
for common ARM zImage support.
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 68f39e74fbc3e58ad52d008072bddacc9eee1c7e |
|
15-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Split plat/mmc.h into local headers and platform_data
We need to remove this from plat for ARM common zImage
support.
Also remove includes not needed by the omap_hsmmc.c driver.
Cc: linux-mmc@vger.kernel.org
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Venkatraman S <svenkatr@ti.com>
[tony@atomide.com: fold in removal of unused driver includes]
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 732231a7c04f334e69af89454073f7a23405468b |
|
20-Sep-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Make omap-wakeupgen.h local
This can be local to mach-omap2.
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| dbc04161048dd5e5c3c58546688a0cc0854051e9 |
|
31-Aug-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+
As the plat and mach includes need to disappear for single zImage work,
we need to remove plat/hardware.h.
Do this by splitting plat/hardware.h into omap1 and omap2+ specific files.
The old plat/hardware.h already has omap1 only defines, so it gets moved
to mach/hardware.h for omap1. For omap2+, we use the local soc.h
that for now just includes the related SoC headers to keep this patch more
readable.
Note that the local soc.h still includes plat/cpu.h that can be dealt
with in later patches. Let's also include plat/serial.h from common.h for
all the board-*.c files. This allows making the include files local later
on without patching these files again.
Note that only minimal changes are done in this patch for the
drivers/watchdog/omap_wdt.c driver to keep things compiling. Further
patches are needed to eventually remove cpu_is_omap usage in the drivers.
Also only minimal changes are done to sound/soc/omap/* to remove the
unneeded includes and to define OMAP44XX_MCPDM_L3_BASE locally so there's
no need to include omap44xx.h.
While at it, also sort some of the includes in the standard way.
Cc: linux-watchdog@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Jarkko Nikula <jarkko.nikula@bitmer.com>
Cc: Liam Girdwood <lrg@ti.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 7d7e1eba7e92c2f9c76db80adc24836e7a114bfb |
|
28-Aug-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Prepare for irqs.h removal
As the interrupts should only be defined in the platform_data, and
eventually coming from device tree, there's no need to define them
in header files.
Let's remove the hardcoded references to irqs.h and fix up the includes
so we don't rely on headers included in irqs.h. Note that we're
defining OMAP_INTC_START as 0 to the interrupts. This will be needed
when we enable SPARSE_IRQ. For some drivers we need to add
#include <plat/cpu.h> for now until these drivers are fixed to
remove cpu_is_omapxxxx() usage.
While at it, sort som of the includes the standard way, and add
the trailing commas where they are missing in the related data
structures.
Note that for drivers/staging/tidspbridge we just define things
locally.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 926fd45ba9eeb4c3d0454b934161ee884dd82a22 |
|
04-Jul-2012 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Add L2 Cache Controller in Device Tree
Provide PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
|
| 0c1b6fac9416a4b662f5b23572729120b7ae8074 |
|
09-May-2012 |
R Sricharan <r.sricharan@ti.com> |
ARM: OMAP5: board-generic: Add device tree support
Adding the minimal support for OMAP5 evm board
with device tree.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| c4082d499fa2c90c089830700e34b64e3b924bb8 |
|
05-Jun-2012 |
R Sricharan <r.sricharan@ti.com> |
ARM: omap2+: board-generic: clean up the irq data from board file
Move the irq_match arrays and the irq init functions of OMAP 2,3
and 4 based boards out of board-generic.c file and also rename the
irq init function to match the interrupt controller present in
the SOCs.
This is a preparatory patch to add the OMAP5 evm board's irq init
support with device tree.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| 1ee47b0ae83e3cae2f9362113b3935898fdb3ea9 |
|
25-Apr-2012 |
Balaji T K <balajitk@ti.com> |
ARM: OMAP4: hsmmc: check for null pointer
platform_device pdev can be NULL if CONFIG_MMC_OMAP_HS is not set.
Add check for NULL pointer. while at it move the duplicated functions
to omap4-common.c
Fixes the following boot crash seen with omap4sdp and omap4panda
when MMC is disabled.
Unable to handle kernel NULL pointer dereference at virtual address 0000008c
pgd = c0004000
[0000008c] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 Not tainted (3.4.0-rc1-05971-ga4dfa82 #4)
PC is at omap_4430sdp_init+0x184/0x410
LR is at device_add+0x1a0/0x664
Signed-off-by: Balaji T K <balajitk@ti.com>
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| cc4ad9072cce2bf0eeae1fb197e42612fbac1f15 |
|
02-Mar-2012 |
R Sricharan <r.sricharan@ti.com> |
ARM: OMAP2+: Fix module build errors with CONFIG_OMAP4_ERRATA_I688
While building modules with randconfig the below errors are observed.
ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined!
ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined!
ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined!
ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined!
ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined!
ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined!
ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined!
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 2ec1fc4e169acc0b8d6733ff028fd52e766773d9 |
|
02-Feb-2012 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Move the barrier memboclk_steal() as part of reserve callback
arm_memblock_steal() is not suppose to be used outside ->reserve callback.
OMAP barrier errata code was using it outside reserve callback and hence
it was broken.
Move the allocation as part of ->reserve callback to fix the it.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 716a3dc20084da9b3ab17bd125005a5345e23e3b |
|
13-Jan-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Add arm_memblock_steal() to allocate memory away from the kernel
Several platforms are now using the memblock_alloc+memblock_free+
memblock_remove trick to obtain memory which won't be mapped in the
kernel's page tables. Most platforms do this (correctly) in the
->reserve callback. However, OMAP has started to call these functions
outside of this callback, and this is extremely unsafe - memory will
not be unmapped, and could well be given out after memblock is no
longer responsible for its management.
So, provide arm_memblock_steal() to perform this function, and ensure
that it panic()s if it is used inappropriately. Convert everyone
over, including OMAP.
As a result, OMAP with OMAP4_ERRATA_I688 enabled will panic on boot
with this change. Mark this option as BROKEN and make it depend on
BROKEN. OMAP needs to be fixed, or 137d105d50 (ARM: OMAP4: Fix
errata i688 with MPU interconnect barriers.) reverted until such
time it can be fixed correctly.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 137d105d50f6e6c373c1aa759f59045e6239cf66 |
|
26-Jun-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.
On OMAP4 SOC, intecronnects has many write buffers in the async bridges
and they need to be drained before CPU enters into standby state.
Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support
but OMAP errata i688 (Async Bridge Corruption) needs to be taken
care to avoid issues like system freeze, CPU deadlocks, random
crashes with register accesses, synchronisation loss on initiators
operating on both interconnect port simultaneously.
As per the errata, if a data is stalled inside asynchronous bridge
because of back pressure, it may be accepted multiple times, creating
pointer misalignment that will corrupt next transfers on that data
path until next reset of the system (No recovery procedure once
the issue is hit, the path remains consistently broken).
Async bridge can be found on path between MPU to EMIF and
MPU to L3 interconnect. This situation can happen only when the
idle is initiated by a Master Request Disconnection (which is
trigged by software when executing WFI on CPU).
The work-around for this errata needs all the initiators
connected through async bridge must ensure that data path
is properly drained before issuing WFI. This condition will be
met if one Strongly ordered access is performed to the
target right before executing the WFI. In MPU case, L3 T2ASYNC
FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure
that there is no synchronisation loss on initiators operating
on both interconnect port simultaneously.
Thanks to Russell for a tip to conver assembly function to
C fuction there by reducing 40 odd lines of code from the patch.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| fcf6efa3ffbc3cc19e7abe39e0b90f497df2fc42 |
|
16-Jun-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Add WakeupGen module as OMAP gic_arch_extn
OMAP WakeupGen is the interrupt controller extension used along
with ARM GIC to wake the CPU out from low power states on
external interrupts.
The WakeupGen unit is responsible for generating the wakeup event
from the incoming interrupts and enable bits. It is implemented
in the MPU always ON power domain. During normal operation,
WakeupGen delivers the external interrupts directly to the GIC.
WakeupGen specification has one restriction as per Veyron version 1.6.
It is SW responsibility to program interrupt enabling/disabling
coherently in the GIC and in the WakeupGen enable registers. That is, a
given interrupt for a given CPU is either enable at both GIC and WakeupGen,
or disable at both, but no mix. That's the reason the WakeupGen is
implemented as an extension of GIC.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| 501f0c751de06d8484b4279131c26f58bd49a69d |
|
01-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: PM: Add SAR RAM support
This patch adds SAR RAM support on OMAP4430. SAR RAM used to save
and restore the HW context in low power modes.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| 02afe8a7f23d562cec76743ae34c4735d2819345 |
|
03-Mar-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Export omap4_get_base*() rather than global address pointers
This patch exports APIs to get base address for GIC
distributor, CPU interface, SCU and PL310 L2 Cache which
are used in OMAP4 PM code.
This was suggested by Kevin Hilman <khilman@ti.com> during
OMAP4 PM code review.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| 0db1803e4ee459fd261915a2f1b2c39bb34767eb |
|
03-Mar-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exit
OMAP4 L2X0 initialisation code uses BUG_ON() for the ioremap()
failure scenarios.
Use WARN_ON() instead and allow graceful function exits.
This was suggsted by Kevin Hilman <khilman@ti.com> during
OMAP4 PM code review.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
|
| 4e65331c6bb4a777bd61a4dac0daa9fc47777b63 |
|
10-Nov-2011 |
Tony Lindgren <tony@atomide.com> |
ARM: 7159/1: OMAP: Introduce local common.h files
As suggested by Russell King - ARM Linux <linux@arm.linux.org.uk>,
there's no need to keep local prototypes in non-local headers.
Add mach-omap1/common.h and mach-omap2/common.h and move the
local prototypes there from plat/common.h and mach/omap4-common.h.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| ab65be268adaae59da5b1306b425a7859f955669 |
|
15-Nov-2011 |
Marc Zyngier <marc.zyngier@arm.com> |
ARM: omap2plus: remove irq-related global base addresses
After the MULTI_IRQ_HANDLER conversion, a couple of global
variables can be removed.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
| 741e3a89dee8a17aa9373975d51f130a65e1683d |
|
17-May-2011 |
Tony Lindgren <tony@atomide.com> |
omap: Use separate init_irq functions to avoid cpu_is_omap tests early
This allows us to remove cpu_is_omap calls from init_irq functions.
There should not be any need for cpu_is_omap calls as at this point.
During the timer init we only care about SoC generation, and not about
subrevisions.
The main reason for the patch is that we want to initialize only
minimal omap specific code from the init_early call.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
|
| 4bdb157749a0da065e532f2f46040c178075b06f |
|
22-Feb-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
ARM: 6755/1: omap4: l2x0: Populate set_debug() function and enable Errata 727915
Populate the l2x0 set_debug function pointer with OMAP secure call
and enable the PL310 Errata 727915
This patch has dependency on the earlier patch
ARM: l2x0: Errata fix for flush by Way operation can cause data
corruption
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| b89cd71a159b5edca4c429687e4af01708eb1b26 |
|
19-Nov-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
omap4: l2x0: Enable early BRESP bit
The AXI protocol specifies that the write response can only
be sent back to an AXI master when the last write data has been
accepted. This optimization enables the PL310 to send the write
response of certain write transactions as soon as the store buffer
accepts the write address. This behavior is not compatible with
the AXI protocol and is disabled by default. You enable this
optimization by setting the Early BRESP Enable bit in the
Auxiliary Control Register (bit [30]).
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| b0f20ff9d7e347c284ea7718597c978a2969ad7b |
|
19-Nov-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
omap4: l2x0: Set share override bit
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 11e0264046e00544eb044fafc27125babd105e41 |
|
19-Nov-2010 |
Mans Rullgard <mans@mansr.com> |
omap4: l2x0: enable instruction and data prefetching
Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.
What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.
Measurement Data:
==
STOCK 10.10 WITHOUT PATCH
========================
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy libc 133 MB/s
copy Android v5 273 MB/s
copy Android NEON 235 MB/s
copy INT32 116 MB/s
copy ASM ARM 187 MB/s
copy ASM VLDM 64 204 MB/s
copy ASM VLDM 128 173 MB/s
copy ASM VLD1 216 MB/s
read ASM ARM 286 MB/s
read ASM VLDM 242 MB/s
read ASM VLD1 286 MB/s
write libc 1947 MB/s
write ASM ARM 1943 MB/s
write ASM VSTM 1942 MB/s
write ASM VST1 1935 MB/s
10.10 + PATCH
=============
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2ab17000 0x2b317000
copy libc 129 MB/s
copy Android v5 256 MB/s
copy Android NEON 356 MB/s
copy INT32 127 MB/s
copy ASM ARM 321 MB/s
copy ASM VLDM 64 337 MB/s
copy ASM VLDM 128 321 MB/s
copy ASM VLD1 350 MB/s
read ASM ARM 496 MB/s
read ASM VLDM 470 MB/s
read ASM VLD1 488 MB/s
write libc 1701 MB/s
write ASM ARM 1682 MB/s
write ASM VSTM 1693 MB/s
write ASM VST1 1681 MB/s
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| 1773e60a816b28f4084810f96e9195aaaa7fb8c3 |
|
19-Nov-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
omap4: l2x0: Construct the AUXCTRL value using defines
This patch removes the hardcoded value of auxctrl value and
construct it using bitfields
Bit 25 is reserved and is always set to 1. Same value
of this bit is retained in this patch
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|
| ff2e27ae0b17f53a6a289c87d325f706598f3788 |
|
04-Dec-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt. Move this into the common GIC code.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| b580b899dd05a007ad232ee49a07b32d91876462 |
|
04-Dec-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: GIC: provide a single initialization function for boot CPU
Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 4e803c40b33822b52389952040f490e79973e94a |
|
31-Jul-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
omap4: l2x0: Override the default l2x0_disable
The machine_kexec() calls outer_disable which can crash on OMAP4
becasue of trustzone restrictions.
This patch overrides the default l2x0_disable with a OMAP4
specific implementation taking care of trustzone
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
|
| a777b7277ef9b04481d4ceaac353bb4bd82e2f1e |
|
16-Sep-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
omap4: l2x0: Fix init parameter for es2.0
On ES2.0 the L2 cache init parameter ineeds to be changed to take
care of cache size. The cache size is 1MB on ES2.0 vs 512KB on ES1.0
This patch fixes the init parameter to update the same using
dynamic cpu version check
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
| fbc9be106e9f27450ea999da74bc24fad04cf41d |
|
14-May-2010 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
omap4: Move SOC specific code from board file
This patch moves OMAP4 soc specific code from 4430sdp board file.
The change is necessary so that newer board support can be added
with minimal changes. This will be also problematic for
multi-board, multi-omap builds.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
|