1/* 2 * OMAP Voltage Controller (VC) interface 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10#include <linux/kernel.h> 11#include <linux/delay.h> 12#include <linux/init.h> 13#include <linux/bug.h> 14#include <linux/io.h> 15 16#include <asm/div64.h> 17 18#include "iomap.h" 19#include "soc.h" 20#include "voltage.h" 21#include "vc.h" 22#include "prm-regbits-34xx.h" 23#include "prm-regbits-44xx.h" 24#include "prm44xx.h" 25#include "pm.h" 26#include "scrm44xx.h" 27#include "control.h" 28 29/** 30 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield 31 * @sa: bit for slave address 32 * @rav: bit for voltage configuration register 33 * @rac: bit for command configuration register 34 * @racen: enable bit for RAC 35 * @cmd: bit for command value set selection 36 * 37 * Channel configuration bits, common for OMAP3+ 38 * OMAP3 register: PRM_VC_CH_CONF 39 * OMAP4 register: PRM_VC_CFG_CHANNEL 40 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG 41 */ 42struct omap_vc_channel_cfg { 43 u8 sa; 44 u8 rav; 45 u8 rac; 46 u8 racen; 47 u8 cmd; 48}; 49 50static struct omap_vc_channel_cfg vc_default_channel_cfg = { 51 .sa = BIT(0), 52 .rav = BIT(1), 53 .rac = BIT(2), 54 .racen = BIT(3), 55 .cmd = BIT(4), 56}; 57 58/* 59 * On OMAP3+, all VC channels have the above default bitfield 60 * configuration, except the OMAP4 MPU channel. This appears 61 * to be a freak accident as every other VC channel has the 62 * default configuration, thus creating a mutant channel config. 63 */ 64static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { 65 .sa = BIT(0), 66 .rav = BIT(2), 67 .rac = BIT(3), 68 .racen = BIT(4), 69 .cmd = BIT(1), 70}; 71 72static struct omap_vc_channel_cfg *vc_cfg_bits; 73 74/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */ 75static u32 sr_i2c_pcb_length = 63; 76#define CFG_CHANNEL_MASK 0x1f 77 78/** 79 * omap_vc_config_channel - configure VC channel to PMIC mappings 80 * @voltdm: pointer to voltagdomain defining the desired VC channel 81 * 82 * Configures the VC channel to PMIC mappings for the following 83 * PMIC settings 84 * - i2c slave address (SA) 85 * - voltage configuration address (RAV) 86 * - command configuration address (RAC) and enable bit (RACEN) 87 * - command values for ON, ONLP, RET and OFF (CMD) 88 * 89 * This function currently only allows flexible configuration of the 90 * non-default channel. Starting with OMAP4, there are more than 2 91 * channels, with one defined as the default (on OMAP4, it's MPU.) 92 * Only the non-default channel can be configured. 93 */ 94static int omap_vc_config_channel(struct voltagedomain *voltdm) 95{ 96 struct omap_vc_channel *vc = voltdm->vc; 97 98 /* 99 * For default channel, the only configurable bit is RACEN. 100 * All others must stay at zero (see function comment above.) 101 */ 102 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) 103 vc->cfg_channel &= vc_cfg_bits->racen; 104 105 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, 106 vc->cfg_channel << vc->cfg_channel_sa_shift, 107 vc->cfg_channel_reg); 108 109 return 0; 110} 111 112/* Voltage scale and accessory APIs */ 113int omap_vc_pre_scale(struct voltagedomain *voltdm, 114 unsigned long target_volt, 115 u8 *target_vsel, u8 *current_vsel) 116{ 117 struct omap_vc_channel *vc = voltdm->vc; 118 u32 vc_cmdval; 119 120 /* Check if sufficient pmic info is available for this vdd */ 121 if (!voltdm->pmic) { 122 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", 123 __func__, voltdm->name); 124 return -EINVAL; 125 } 126 127 if (!voltdm->pmic->uv_to_vsel) { 128 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", 129 __func__, voltdm->name); 130 return -ENODATA; 131 } 132 133 if (!voltdm->read || !voltdm->write) { 134 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 135 __func__, voltdm->name); 136 return -EINVAL; 137 } 138 139 *target_vsel = voltdm->pmic->uv_to_vsel(target_volt); 140 *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); 141 142 /* Setting the ON voltage to the new target voltage */ 143 vc_cmdval = voltdm->read(vc->cmdval_reg); 144 vc_cmdval &= ~vc->common->cmd_on_mask; 145 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); 146 voltdm->write(vc_cmdval, vc->cmdval_reg); 147 148 voltdm->vc_param->on = target_volt; 149 150 omap_vp_update_errorgain(voltdm, target_volt); 151 152 return 0; 153} 154 155void omap_vc_post_scale(struct voltagedomain *voltdm, 156 unsigned long target_volt, 157 u8 target_vsel, u8 current_vsel) 158{ 159 u32 smps_steps = 0, smps_delay = 0; 160 161 smps_steps = abs(target_vsel - current_vsel); 162 /* SMPS slew rate / step size. 2us added as buffer. */ 163 smps_delay = ((smps_steps * voltdm->pmic->step_size) / 164 voltdm->pmic->slew_rate) + 2; 165 udelay(smps_delay); 166} 167 168/* vc_bypass_scale - VC bypass method of voltage scaling */ 169int omap_vc_bypass_scale(struct voltagedomain *voltdm, 170 unsigned long target_volt) 171{ 172 struct omap_vc_channel *vc = voltdm->vc; 173 u32 loop_cnt = 0, retries_cnt = 0; 174 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; 175 u8 target_vsel, current_vsel; 176 int ret; 177 178 ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); 179 if (ret) 180 return ret; 181 182 vc_valid = vc->common->valid; 183 vc_bypass_val_reg = vc->common->bypass_val_reg; 184 vc_bypass_value = (target_vsel << vc->common->data_shift) | 185 (vc->volt_reg_addr << vc->common->regaddr_shift) | 186 (vc->i2c_slave_addr << vc->common->slaveaddr_shift); 187 188 voltdm->write(vc_bypass_value, vc_bypass_val_reg); 189 voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); 190 191 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 192 /* 193 * Loop till the bypass command is acknowledged from the SMPS. 194 * NOTE: This is legacy code. The loop count and retry count needs 195 * to be revisited. 196 */ 197 while (!(vc_bypass_value & vc_valid)) { 198 loop_cnt++; 199 200 if (retries_cnt > 10) { 201 pr_warn("%s: Retry count exceeded\n", __func__); 202 return -ETIMEDOUT; 203 } 204 205 if (loop_cnt > 50) { 206 retries_cnt++; 207 loop_cnt = 0; 208 udelay(10); 209 } 210 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 211 } 212 213 omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); 214 return 0; 215} 216 217/* Convert microsecond value to number of 32kHz clock cycles */ 218static inline u32 omap_usec_to_32k(u32 usec) 219{ 220 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); 221} 222 223struct omap3_vc_timings { 224 u32 voltsetup1; 225 u32 voltsetup2; 226}; 227 228struct omap3_vc { 229 struct voltagedomain *vd; 230 u32 voltctrl; 231 u32 voltsetup1; 232 u32 voltsetup2; 233 struct omap3_vc_timings timings[2]; 234}; 235static struct omap3_vc vc; 236 237void omap3_vc_set_pmic_signaling(int core_next_state) 238{ 239 struct voltagedomain *vd = vc.vd; 240 struct omap3_vc_timings *c = vc.timings; 241 u32 voltctrl, voltsetup1, voltsetup2; 242 243 voltctrl = vc.voltctrl; 244 voltsetup1 = vc.voltsetup1; 245 voltsetup2 = vc.voltsetup2; 246 247 switch (core_next_state) { 248 case PWRDM_POWER_OFF: 249 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | 250 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); 251 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; 252 if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF) 253 voltsetup2 = c->voltsetup2; 254 else 255 voltsetup1 = c->voltsetup1; 256 break; 257 case PWRDM_POWER_RET: 258 default: 259 c++; 260 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | 261 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); 262 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; 263 voltsetup1 = c->voltsetup1; 264 break; 265 } 266 267 if (voltctrl != vc.voltctrl) { 268 vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); 269 vc.voltctrl = voltctrl; 270 } 271 if (voltsetup1 != vc.voltsetup1) { 272 vd->write(c->voltsetup1, 273 OMAP3_PRM_VOLTSETUP1_OFFSET); 274 vc.voltsetup1 = voltsetup1; 275 } 276 if (voltsetup2 != vc.voltsetup2) { 277 vd->write(c->voltsetup2, 278 OMAP3_PRM_VOLTSETUP2_OFFSET); 279 vc.voltsetup2 = voltsetup2; 280 } 281} 282 283#define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \ 284 OMAP3430_PRM_POLCTRL_CLKREQ_POL) 285#define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL 286 287/* 288 * Configure signal polarity for sys_clkreq and sys_off_mode pins 289 * as the default values are wrong and can cause the system to hang 290 * if any twl4030 scripts are loaded. 291 */ 292static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) 293{ 294 u32 val; 295 296 if (vc.vd) 297 return; 298 299 vc.vd = voltdm; 300 301 val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); 302 if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || 303 (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) { 304 val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; 305 val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; 306 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n", 307 val); 308 voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); 309 } 310 311 /* 312 * By default let's use I2C4 signaling for retention idle 313 * and sys_off_mode pin signaling for off idle. This way we 314 * have sys_clk_req pin go down for retention and both 315 * sys_clk_req and sys_off_mode pins will go down for off 316 * idle. And we can also scale voltages to zero for off-idle. 317 * Note that no actual voltage scaling during off-idle will 318 * happen unless the board specific twl4030 PMIC scripts are 319 * loaded. 320 */ 321 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); 322 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { 323 val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; 324 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n", 325 val); 326 voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); 327 } 328 vc.voltctrl = val; 329 330 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); 331} 332 333static void omap3_init_voltsetup1(struct voltagedomain *voltdm, 334 struct omap3_vc_timings *c, u32 idle) 335{ 336 unsigned long val; 337 338 val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; 339 val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; 340 val <<= __ffs(voltdm->vfsm->voltsetup_mask); 341 c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; 342 c->voltsetup1 |= val; 343} 344 345/** 346 * omap3_set_i2c_timings - sets i2c sleep timings for a channel 347 * @voltdm: channel to configure 348 * @off_mode: select whether retention or off mode values used 349 * 350 * Calculates and sets up voltage controller to use I2C based 351 * voltage scaling for sleep modes. This can be used for either off mode 352 * or retention. Off mode has additionally an option to use sys_off_mode 353 * pad, which uses a global signal to program the whole power IC to 354 * off-mode. 355 * 356 * Note that pmic is not controlling the voltage scaling during 357 * retention signaled over I2C4, so we can keep voltsetup2 as 0. 358 * And the oscillator is not shut off over I2C4, so no need to 359 * set clksetup. 360 */ 361static void omap3_set_i2c_timings(struct voltagedomain *voltdm) 362{ 363 struct omap3_vc_timings *c = vc.timings; 364 365 /* Configure PRWDM_POWER_OFF over I2C4 */ 366 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off); 367 c++; 368 /* Configure PRWDM_POWER_RET over I2C4 */ 369 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret); 370} 371 372/** 373 * omap3_set_off_timings - sets off-mode timings for a channel 374 * @voltdm: channel to configure 375 * 376 * Calculates and sets up off-mode timings for a channel. Off-mode 377 * can use either I2C based voltage scaling, or alternatively 378 * sys_off_mode pad can be used to send a global command to power IC.n, 379 * sys_off_mode has the additional benefit that voltages can be 380 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only 381 * scale to 600mV. 382 * 383 * Note that omap is not controlling the voltage scaling during 384 * off idle signaled by sys_off_mode, so we can keep voltsetup1 385 * as 0. 386 */ 387static void omap3_set_off_timings(struct voltagedomain *voltdm) 388{ 389 struct omap3_vc_timings *c = vc.timings; 390 u32 tstart, tshut, clksetup, voltoffset; 391 392 if (c->voltsetup2) 393 return; 394 395 omap_pm_get_oscillator(&tstart, &tshut); 396 if (tstart == ULONG_MAX) { 397 pr_debug("PM: oscillator start-up time not initialized, using 10ms\n"); 398 clksetup = omap_usec_to_32k(10000); 399 } else { 400 clksetup = omap_usec_to_32k(tstart); 401 } 402 403 /* 404 * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to 405 * switch from HFCLKIN to internal oscillator. That means timings 406 * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And 407 * that means we can calculate the value based on the oscillator 408 * start-up time since voltoffset2 = clksetup - voltoffset. 409 */ 410 voltoffset = omap_usec_to_32k(488); 411 c->voltsetup2 = clksetup - voltoffset; 412 voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET); 413 voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET); 414} 415 416static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) 417{ 418 omap3_vc_init_pmic_signaling(voltdm); 419 omap3_set_off_timings(voltdm); 420 omap3_set_i2c_timings(voltdm); 421} 422 423/** 424 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4 425 * @voltdm: channel to calculate values for 426 * @voltage_diff: voltage difference in microvolts 427 * 428 * Calculates voltage ramp prescaler + counter values for a voltage 429 * difference on omap4. Returns a field value suitable for writing to 430 * VOLTSETUP register for a channel in following format: 431 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference. 432 */ 433static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff) 434{ 435 u32 prescaler; 436 u32 cycles; 437 u32 time; 438 439 time = voltage_diff / voltdm->pmic->slew_rate; 440 441 cycles = voltdm->sys_clk.rate / 1000 * time / 1000; 442 443 cycles /= 64; 444 prescaler = 0; 445 446 /* shift to next prescaler until no overflow */ 447 448 /* scale for div 256 = 64 * 4 */ 449 if (cycles > 63) { 450 cycles /= 4; 451 prescaler++; 452 } 453 454 /* scale for div 512 = 256 * 2 */ 455 if (cycles > 63) { 456 cycles /= 2; 457 prescaler++; 458 } 459 460 /* scale for div 2048 = 512 * 4 */ 461 if (cycles > 63) { 462 cycles /= 4; 463 prescaler++; 464 } 465 466 /* check for overflow => invalid ramp time */ 467 if (cycles > 63) { 468 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__, 469 voltdm->name); 470 return 0; 471 } 472 473 cycles++; 474 475 return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) | 476 (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT); 477} 478 479/** 480 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield 481 * @usec: microseconds 482 * @shift: number of bits to shift left 483 * @mask: bitfield mask 484 * 485 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is 486 * shifted to requested position, and checked agains the mask value. 487 * If larger, forced to the max value of the field (i.e. the mask itself.) 488 * Returns the SCRM bitfield value. 489 */ 490static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask) 491{ 492 u32 val; 493 494 val = omap_usec_to_32k(usec) << shift; 495 496 /* Check for overflow, if yes, force to max value */ 497 if (val > mask) 498 val = mask; 499 500 return val; 501} 502 503/** 504 * omap4_set_timings - set voltage ramp timings for a channel 505 * @voltdm: channel to configure 506 * @off_mode: whether off-mode values are used 507 * 508 * Calculates and sets the voltage ramp up / down values for a channel. 509 */ 510static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode) 511{ 512 u32 val; 513 u32 ramp; 514 int offset; 515 u32 tstart, tshut; 516 517 if (off_mode) { 518 ramp = omap4_calc_volt_ramp(voltdm, 519 voltdm->vc_param->on - voltdm->vc_param->off); 520 offset = voltdm->vfsm->voltsetup_off_reg; 521 } else { 522 ramp = omap4_calc_volt_ramp(voltdm, 523 voltdm->vc_param->on - voltdm->vc_param->ret); 524 offset = voltdm->vfsm->voltsetup_reg; 525 } 526 527 if (!ramp) 528 return; 529 530 val = voltdm->read(offset); 531 532 val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT; 533 534 val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT; 535 536 voltdm->write(val, offset); 537 538 omap_pm_get_oscillator(&tstart, &tshut); 539 540 val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT, 541 OMAP4_SETUPTIME_MASK); 542 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, 543 OMAP4_DOWNTIME_MASK); 544 545 writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); 546} 547 548/* OMAP4 specific voltage init functions */ 549static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) 550{ 551 omap4_set_timings(voltdm, true); 552 omap4_set_timings(voltdm, false); 553} 554 555struct i2c_init_data { 556 u8 loadbits; 557 u8 load; 558 u8 hsscll_38_4; 559 u8 hsscll_26; 560 u8 hsscll_19_2; 561 u8 hsscll_16_8; 562 u8 hsscll_12; 563}; 564 565static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = { 566 { 567 .load = 50, 568 .loadbits = 0x3, 569 .hsscll_38_4 = 13, 570 .hsscll_26 = 11, 571 .hsscll_19_2 = 9, 572 .hsscll_16_8 = 9, 573 .hsscll_12 = 8, 574 }, 575 { 576 .load = 25, 577 .loadbits = 0x2, 578 .hsscll_38_4 = 13, 579 .hsscll_26 = 11, 580 .hsscll_19_2 = 9, 581 .hsscll_16_8 = 9, 582 .hsscll_12 = 8, 583 }, 584 { 585 .load = 12, 586 .loadbits = 0x1, 587 .hsscll_38_4 = 11, 588 .hsscll_26 = 10, 589 .hsscll_19_2 = 9, 590 .hsscll_16_8 = 9, 591 .hsscll_12 = 8, 592 }, 593 { 594 .load = 0, 595 .loadbits = 0x0, 596 .hsscll_38_4 = 12, 597 .hsscll_26 = 10, 598 .hsscll_19_2 = 9, 599 .hsscll_16_8 = 8, 600 .hsscll_12 = 8, 601 }, 602}; 603 604/** 605 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters 606 * @voltdm: voltagedomain pointer to get data from 607 * 608 * Use PMIC + board supplied settings for calculating the total I2C 609 * channel capacitance and set the timing parameters based on this. 610 * Pre-calculated values are provided in data tables, as it is not 611 * too straightforward to calculate these runtime. 612 */ 613static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm) 614{ 615 u32 capacitance; 616 u32 val; 617 u16 hsscll; 618 const struct i2c_init_data *i2c_data; 619 620 if (!voltdm->pmic->i2c_high_speed) { 621 pr_warn("%s: only high speed supported!\n", __func__); 622 return; 623 } 624 625 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */ 626 capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8); 627 628 /* OMAP pad capacitance */ 629 capacitance += 4; 630 631 /* PMIC pad capacitance */ 632 capacitance += voltdm->pmic->i2c_pad_load; 633 634 /* Search for capacitance match in the table */ 635 i2c_data = omap4_i2c_timing_data; 636 637 while (i2c_data->load > capacitance) 638 i2c_data++; 639 640 /* Select proper values based on sysclk frequency */ 641 switch (voltdm->sys_clk.rate) { 642 case 38400000: 643 hsscll = i2c_data->hsscll_38_4; 644 break; 645 case 26000000: 646 hsscll = i2c_data->hsscll_26; 647 break; 648 case 19200000: 649 hsscll = i2c_data->hsscll_19_2; 650 break; 651 case 16800000: 652 hsscll = i2c_data->hsscll_16_8; 653 break; 654 case 12000000: 655 hsscll = i2c_data->hsscll_12; 656 break; 657 default: 658 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__, 659 voltdm->sys_clk.rate); 660 return; 661 } 662 663 /* Loadbits define pull setup for the I2C channels */ 664 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; 665 666 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ 667 writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + 668 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); 669 670 /* HSSCLH can always be zero */ 671 val = hsscll << OMAP4430_HSSCLL_SHIFT; 672 val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT); 673 674 /* Write setup times to I2C config register */ 675 voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); 676} 677 678 679 680/** 681 * omap_vc_i2c_init - initialize I2C interface to PMIC 682 * @voltdm: voltage domain containing VC data 683 * 684 * Use PMIC supplied settings for I2C high-speed mode and 685 * master code (if set) and program the VC I2C configuration 686 * register. 687 * 688 * The VC I2C configuration is common to all VC channels, 689 * so this function only configures I2C for the first VC 690 * channel registers. All other VC channels will use the 691 * same configuration. 692 */ 693static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) 694{ 695 struct omap_vc_channel *vc = voltdm->vc; 696 static bool initialized; 697 static bool i2c_high_speed; 698 u8 mcode; 699 700 if (initialized) { 701 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 702 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n", 703 __func__, voltdm->name, i2c_high_speed); 704 return; 705 } 706 707 i2c_high_speed = voltdm->pmic->i2c_high_speed; 708 if (i2c_high_speed) 709 voltdm->rmw(vc->common->i2c_cfg_hsen_mask, 710 vc->common->i2c_cfg_hsen_mask, 711 vc->common->i2c_cfg_reg); 712 713 mcode = voltdm->pmic->i2c_mcode; 714 if (mcode) 715 voltdm->rmw(vc->common->i2c_mcode_mask, 716 mcode << __ffs(vc->common->i2c_mcode_mask), 717 vc->common->i2c_cfg_reg); 718 719 if (cpu_is_omap44xx()) 720 omap4_vc_i2c_timing_init(voltdm); 721 722 initialized = true; 723} 724 725/** 726 * omap_vc_calc_vsel - calculate vsel value for a channel 727 * @voltdm: channel to calculate value for 728 * @uvolt: microvolt value to convert to vsel 729 * 730 * Converts a microvolt value to vsel value for the used PMIC. 731 * This checks whether the microvolt value is out of bounds, and 732 * adjusts the value accordingly. If unsupported value detected, 733 * warning is thrown. 734 */ 735static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) 736{ 737 if (voltdm->pmic->vddmin > uvolt) 738 uvolt = voltdm->pmic->vddmin; 739 if (voltdm->pmic->vddmax < uvolt) { 740 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n", 741 __func__, uvolt, voltdm->pmic->vddmax); 742 /* Lets try maximum value anyway */ 743 uvolt = voltdm->pmic->vddmax; 744 } 745 746 return voltdm->pmic->uv_to_vsel(uvolt); 747} 748 749#ifdef CONFIG_PM 750/** 751 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB 752 * @mm: length of the PCB trace in millimetres 753 * 754 * Sets the PCB trace length for the I2C channel. By default uses 63mm. 755 * This is needed for properly calculating the capacitance value for 756 * the PCB trace, and for setting the SR I2C channel timing parameters. 757 */ 758void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm) 759{ 760 sr_i2c_pcb_length = mm; 761} 762#endif 763 764void __init omap_vc_init_channel(struct voltagedomain *voltdm) 765{ 766 struct omap_vc_channel *vc = voltdm->vc; 767 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; 768 u32 val; 769 770 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { 771 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); 772 return; 773 } 774 775 if (!voltdm->read || !voltdm->write) { 776 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 777 __func__, voltdm->name); 778 return; 779 } 780 781 vc->cfg_channel = 0; 782 if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) 783 vc_cfg_bits = &vc_mutant_channel_cfg; 784 else 785 vc_cfg_bits = &vc_default_channel_cfg; 786 787 /* get PMIC/board specific settings */ 788 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; 789 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; 790 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; 791 792 /* Configure the i2c slave address for this VC */ 793 voltdm->rmw(vc->smps_sa_mask, 794 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), 795 vc->smps_sa_reg); 796 vc->cfg_channel |= vc_cfg_bits->sa; 797 798 /* 799 * Configure the PMIC register addresses. 800 */ 801 voltdm->rmw(vc->smps_volra_mask, 802 vc->volt_reg_addr << __ffs(vc->smps_volra_mask), 803 vc->smps_volra_reg); 804 vc->cfg_channel |= vc_cfg_bits->rav; 805 806 if (vc->cmd_reg_addr) { 807 voltdm->rmw(vc->smps_cmdra_mask, 808 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), 809 vc->smps_cmdra_reg); 810 vc->cfg_channel |= vc_cfg_bits->rac; 811 } 812 813 if (vc->cmd_reg_addr == vc->volt_reg_addr) 814 vc->cfg_channel |= vc_cfg_bits->racen; 815 816 /* Set up the on, inactive, retention and off voltage */ 817 on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on); 818 onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp); 819 ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret); 820 off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off); 821 822 val = ((on_vsel << vc->common->cmd_on_shift) | 823 (onlp_vsel << vc->common->cmd_onlp_shift) | 824 (ret_vsel << vc->common->cmd_ret_shift) | 825 (off_vsel << vc->common->cmd_off_shift)); 826 voltdm->write(val, vc->cmdval_reg); 827 vc->cfg_channel |= vc_cfg_bits->cmd; 828 829 /* Channel configuration */ 830 omap_vc_config_channel(voltdm); 831 832 omap_vc_i2c_init(voltdm); 833 834 if (cpu_is_omap34xx()) 835 omap3_vc_init_channel(voltdm); 836 else if (cpu_is_omap44xx()) 837 omap4_vc_init_channel(voltdm); 838} 839 840