1#ifndef __ASM_ARCH_REGS_LCD_H 2#define __ASM_ARCH_REGS_LCD_H 3 4#include <mach/bitfield.h> 5 6/* 7 * LCD Controller Registers and Bits Definitions 8 */ 9#define LCCR0 (0x000) /* LCD Controller Control Register 0 */ 10#define LCCR1 (0x004) /* LCD Controller Control Register 1 */ 11#define LCCR2 (0x008) /* LCD Controller Control Register 2 */ 12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ 13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ 14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ 15#define LCSR (0x038) /* LCD Controller Status Register 0 */ 16#define LCSR1 (0x034) /* LCD Controller Status Register 1 */ 17#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ 18#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ 19#define TMEDCR (0x044) /* TMED Control Register */ 20 21#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ 22#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ 23#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ 24#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ 25#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ 26#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ 27#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ 28 29#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ 30#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ 31#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ 32#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ 33 34#define CMDCR (0x100) /* Command Control Register */ 35#define PRSR (0x104) /* Panel Read Status Register */ 36 37#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) 38 39#define LCCR3_PDFOR_0 (0 << 30) 40#define LCCR3_PDFOR_1 (1 << 30) 41#define LCCR3_PDFOR_2 (2 << 30) 42#define LCCR3_PDFOR_3 (3 << 30) 43 44#define LCCR4_PAL_FOR_0 (0 << 15) 45#define LCCR4_PAL_FOR_1 (1 << 15) 46#define LCCR4_PAL_FOR_2 (2 << 15) 47#define LCCR4_PAL_FOR_3 (3 << 15) 48#define LCCR4_PAL_FOR_MASK (3 << 15) 49 50#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ 51#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ 52#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ 53#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ 54#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ 55#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ 56#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ 57 58#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ 59#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ 60#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 61#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ 62#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ 63#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ 64#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ 65 66#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ 67#define LCCR0_SFM (1 << 4) /* Start of frame mask */ 68#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ 69#define LCCR0_EFM (1 << 6) /* End of Frame mask */ 70#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ 71#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ 72#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ 73#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ 74#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ 75#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ 76#define LCCR0_DIS (1 << 10) /* LCD Disable */ 77#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ 78#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ 79#define LCCR0_PDD_S 12 80#define LCCR0_BM (1 << 20) /* Branch mask */ 81#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ 82#define LCCR0_LCDT (1 << 22) /* LCD panel type */ 83#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ 84#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ 85#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ 86#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ 87 88#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ 89#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) 90 91#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ 92#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) 93 94#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ 95#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) 96 97#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ 98#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) 99 100#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ 101#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) 102 103#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ 104#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) 105 106#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ 107#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) 108 109#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ 110#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) 111 112#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ 113#define LCCR3_API_S 16 114#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ 115#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ 116#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ 117#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ 118#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ 119 120#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ 121#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ 122#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ 123 124#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ 125#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ 126#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) 127 128#define LCCR3_ACB Fld (8, 8) /* AC Bias */ 129#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) 130 131#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ 132#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ 133 134#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ 135#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ 136 137#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ 138#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ 139#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ 140#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ 141 142#define LCSR_LDD (1 << 0) /* LCD Disable Done */ 143#define LCSR_SOF (1 << 1) /* Start of frame */ 144#define LCSR_BER (1 << 2) /* Bus error */ 145#define LCSR_ABC (1 << 3) /* AC Bias count */ 146#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ 147#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ 148#define LCSR_OU (1 << 6) /* output FIFO underrun */ 149#define LCSR_QD (1 << 7) /* quick disable */ 150#define LCSR_EOF (1 << 8) /* end of frame */ 151#define LCSR_BS (1 << 9) /* branch status */ 152#define LCSR_SINT (1 << 10) /* subsequent interrupt */ 153#define LCSR_RD_ST (1 << 11) /* read status */ 154#define LCSR_CMD_INT (1 << 12) /* command interrupt */ 155 156#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ 157#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ 158#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ 159#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ 160 161#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 162 163/* overlay control registers */ 164#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ 165#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ 166#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ 167#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ 168#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ 169#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ 170#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ 171 172/* smartpanel related */ 173#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ 174#define PRSR_A0 (1 << 8) /* Read Data Source */ 175#define PRSR_ST_OK (1 << 9) /* Status OK */ 176#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ 177 178#define SMART_CMD_A0 (0x1 << 8) 179#define SMART_CMD_READ_STATUS_REG (0x0 << 9) 180#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) 181#define SMART_CMD_WRITE_COMMAND (0x1 << 9) 182#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) 183#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) 184#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) 185#define SMART_CMD_NOOP (0x4 << 9) 186#define SMART_CMD_INTERRUPT (0x5 << 9) 187 188#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) 189#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) 190 191/* SMART_DELAY() is introduced for software controlled delay primitive which 192 * can be inserted between command sequences, unused command 0x6 is used here 193 * and delay ranges from 0ms ~ 255ms 194 */ 195#define SMART_CMD_DELAY (0x6 << 9) 196#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) 197#endif /* __ASM_ARCH_REGS_LCD_H */ 198