1/*
2 *  linux/arch/arm/mach-pxa/irq.c
3 *
4 *  Generic PXA IRQ handling
5 *
6 *  Author:	Nicolas Pitre
7 *  Created:	Jun 15, 2001
8 *  Copyright:	MontaVista Software Inc.
9 *
10 *  This program is free software; you can redistribute it and/or modify
11 *  it under the terms of the GNU General Public License version 2 as
12 *  published by the Free Software Foundation.
13 */
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/syscore_ops.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <asm/exception.h>
24
25#include <mach/hardware.h>
26#include <mach/irqs.h>
27
28#include "generic.h"
29
30#define ICIP			(0x000)
31#define ICMR			(0x004)
32#define ICLR			(0x008)
33#define ICFR			(0x00c)
34#define ICPR			(0x010)
35#define ICCR			(0x014)
36#define ICHP			(0x018)
37#define IPR(i)			(((i) < 32) ? (0x01c + ((i) << 2)) :		\
38				((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :	\
39				      (0x144 + (((i) - 64) << 2)))
40#define ICHP_VAL_IRQ		(1 << 31)
41#define ICHP_IRQ(i)		(((i) >> 16) & 0x7fff)
42#define IPR_VALID		(1 << 31)
43#define IRQ_BIT(n)		(((n) - PXA_IRQ(0)) & 0x1f)
44
45#define MAX_INTERNAL_IRQS	128
46
47/*
48 * This is for peripheral IRQs internal to the PXA chip.
49 */
50
51static void __iomem *pxa_irq_base;
52static int pxa_internal_irq_nr;
53static bool cpu_has_ipr;
54
55static inline void __iomem *irq_base(int i)
56{
57	static unsigned long phys_base_offset[] = {
58		0x0,
59		0x9c,
60		0x130,
61	};
62
63	return pxa_irq_base + phys_base_offset[i];
64}
65
66void pxa_mask_irq(struct irq_data *d)
67{
68	void __iomem *base = irq_data_get_irq_chip_data(d);
69	uint32_t icmr = __raw_readl(base + ICMR);
70
71	icmr &= ~(1 << IRQ_BIT(d->irq));
72	__raw_writel(icmr, base + ICMR);
73}
74
75void pxa_unmask_irq(struct irq_data *d)
76{
77	void __iomem *base = irq_data_get_irq_chip_data(d);
78	uint32_t icmr = __raw_readl(base + ICMR);
79
80	icmr |= 1 << IRQ_BIT(d->irq);
81	__raw_writel(icmr, base + ICMR);
82}
83
84static struct irq_chip pxa_internal_irq_chip = {
85	.name		= "SC",
86	.irq_ack	= pxa_mask_irq,
87	.irq_mask	= pxa_mask_irq,
88	.irq_unmask	= pxa_unmask_irq,
89};
90
91asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
92{
93	uint32_t icip, icmr, mask;
94
95	do {
96		icip = __raw_readl(pxa_irq_base + ICIP);
97		icmr = __raw_readl(pxa_irq_base + ICMR);
98		mask = icip & icmr;
99
100		if (mask == 0)
101			break;
102
103		handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
104	} while (1);
105}
106
107asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
108{
109	uint32_t ichp;
110
111	do {
112		__asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
113
114		if ((ichp & ICHP_VAL_IRQ) == 0)
115			break;
116
117		handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
118	} while (1);
119}
120
121void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
122{
123	int irq, i, n;
124
125	BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
126
127	pxa_internal_irq_nr = irq_nr;
128	cpu_has_ipr = !cpu_is_pxa25x();
129	pxa_irq_base = io_p2v(0x40d00000);
130
131	for (n = 0; n < irq_nr; n += 32) {
132		void __iomem *base = irq_base(n >> 5);
133
134		__raw_writel(0, base + ICMR);	/* disable all IRQs */
135		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */
136		for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
137			/* initialize interrupt priority */
138			if (cpu_has_ipr)
139				__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
140
141			irq = PXA_IRQ(i);
142			irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
143						 handle_level_irq);
144			irq_set_chip_data(irq, base);
145			set_irq_flags(irq, IRQF_VALID);
146		}
147	}
148
149	/* only unmasked interrupts kick us out of idle */
150	__raw_writel(1, irq_base(0) + ICCR);
151
152	pxa_internal_irq_chip.irq_set_wake = fn;
153}
154
155#ifdef CONFIG_PM
156static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
157static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
158
159static int pxa_irq_suspend(void)
160{
161	int i;
162
163	for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
164		void __iomem *base = irq_base(i);
165
166		saved_icmr[i] = __raw_readl(base + ICMR);
167		__raw_writel(0, base + ICMR);
168	}
169
170	if (cpu_has_ipr) {
171		for (i = 0; i < pxa_internal_irq_nr; i++)
172			saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
173	}
174
175	return 0;
176}
177
178static void pxa_irq_resume(void)
179{
180	int i;
181
182	for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
183		void __iomem *base = irq_base(i);
184
185		__raw_writel(saved_icmr[i], base + ICMR);
186		__raw_writel(0, base + ICLR);
187	}
188
189	if (cpu_has_ipr)
190		for (i = 0; i < pxa_internal_irq_nr; i++)
191			__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
192
193	__raw_writel(1, pxa_irq_base + ICCR);
194}
195#else
196#define pxa_irq_suspend		NULL
197#define pxa_irq_resume		NULL
198#endif
199
200struct syscore_ops pxa_irq_syscore_ops = {
201	.suspend	= pxa_irq_suspend,
202	.resume		= pxa_irq_resume,
203};
204
205#ifdef CONFIG_OF
206static struct irq_domain *pxa_irq_domain;
207
208static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
209		       irq_hw_number_t hw)
210{
211	void __iomem *base = irq_base(hw / 32);
212
213	/* initialize interrupt priority */
214	if (cpu_has_ipr)
215		__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
216
217	irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
218				 handle_level_irq);
219	irq_set_chip_data(hw, base);
220	set_irq_flags(hw, IRQF_VALID);
221
222	return 0;
223}
224
225static struct irq_domain_ops pxa_irq_ops = {
226	.map    = pxa_irq_map,
227	.xlate  = irq_domain_xlate_onecell,
228};
229
230static const struct of_device_id intc_ids[] __initconst = {
231	{ .compatible = "marvell,pxa-intc", },
232	{}
233};
234
235void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
236{
237	struct device_node *node;
238	struct resource res;
239	int n, ret;
240
241	node = of_find_matching_node(NULL, intc_ids);
242	if (!node) {
243		pr_err("Failed to find interrupt controller in arch-pxa\n");
244		return;
245	}
246
247	ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
248				   &pxa_internal_irq_nr);
249	if (ret) {
250		pr_err("Not found marvell,intc-nr-irqs property\n");
251		return;
252	}
253
254	ret = of_address_to_resource(node, 0, &res);
255	if (ret < 0) {
256		pr_err("No registers defined for node\n");
257		return;
258	}
259	pxa_irq_base = io_p2v(res.start);
260
261	if (of_find_property(node, "marvell,intc-priority", NULL))
262		cpu_has_ipr = 1;
263
264	ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
265	if (ret < 0) {
266		pr_err("Failed to allocate IRQ numbers\n");
267		return;
268	}
269
270	pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
271					       &pxa_irq_ops, NULL);
272	if (!pxa_irq_domain)
273		panic("Unable to add PXA IRQ domain\n");
274
275	irq_set_default_host(pxa_irq_domain);
276
277	for (n = 0; n < pxa_internal_irq_nr; n += 32) {
278		void __iomem *base = irq_base(n >> 5);
279
280		__raw_writel(0, base + ICMR);	/* disable all IRQs */
281		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */
282	}
283
284	/* only unmasked interrupts kick us out of idle */
285	__raw_writel(1, irq_base(0) + ICCR);
286
287	pxa_internal_irq_chip.irq_set_wake = fn;
288}
289#endif /* CONFIG_OF */
290