1/*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013  Renesas Solutions Corp.
5 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013  Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/irqchip/arm-gic.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/platform_data/dma-rcar-hpbdma.h>
28#include <linux/platform_data/gpio-rcar.h>
29#include <linux/platform_data/irq-renesas-intc-irqpin.h>
30#include <linux/platform_device.h>
31#include <linux/irqchip.h>
32#include <linux/serial_sci.h>
33#include <linux/sh_timer.h>
34#include <linux/pm_runtime.h>
35#include <linux/usb/phy.h>
36#include <linux/usb/hcd.h>
37#include <linux/usb/ehci_pdriver.h>
38#include <linux/usb/ohci_pdriver.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/mach/arch.h>
42#include <asm/hardware/cache-l2x0.h>
43
44#include "common.h"
45#include "irqs.h"
46#include "r8a7778.h"
47
48/* SCIF */
49#define R8A7778_SCIF(index, baseaddr, irq)			\
50static struct plat_sci_port scif##index##_platform_data = {	\
51	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
52	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,	\
53	.type		= PORT_SCIF,				\
54};								\
55								\
56static struct resource scif##index##_resources[] = {		\
57	DEFINE_RES_MEM(baseaddr, 0x100),			\
58	DEFINE_RES_IRQ(irq),					\
59}
60
61R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
62R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
63R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
64R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
65R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
66R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
67
68#define r8a7778_register_scif(index)					       \
69	platform_device_register_resndata(NULL, "sh-sci", index,	       \
70					  scif##index##_resources,	       \
71					  ARRAY_SIZE(scif##index##_resources), \
72					  &scif##index##_platform_data,	       \
73					  sizeof(scif##index##_platform_data))
74
75/* TMU */
76static struct sh_timer_config sh_tmu0_platform_data = {
77	.channels_mask = 7,
78};
79
80static struct resource sh_tmu0_resources[] = {
81	DEFINE_RES_MEM(0xffd80000, 0x30),
82	DEFINE_RES_IRQ(gic_iid(0x40)),
83	DEFINE_RES_IRQ(gic_iid(0x41)),
84	DEFINE_RES_IRQ(gic_iid(0x42)),
85};
86
87#define r8a7778_register_tmu(idx)			\
88	platform_device_register_resndata(		\
89		NULL, "sh-tmu", idx,			\
90		sh_tmu##idx##_resources,		\
91		ARRAY_SIZE(sh_tmu##idx##_resources),	\
92		&sh_tmu##idx##_platform_data,		\
93		sizeof(sh_tmu##idx##_platform_data))
94
95int r8a7778_usb_phy_power(bool enable)
96{
97	static struct usb_phy *phy = NULL;
98	int ret = 0;
99
100	if (!phy)
101		phy = usb_get_phy(USB_PHY_TYPE_USB2);
102
103	if (IS_ERR(phy)) {
104		pr_err("kernel doesn't have usb phy driver\n");
105		return PTR_ERR(phy);
106	}
107
108	if (enable)
109		ret = usb_phy_init(phy);
110	else
111		usb_phy_shutdown(phy);
112
113	return ret;
114}
115
116/* USB */
117static int usb_power_on(struct platform_device *pdev)
118{
119	int ret = r8a7778_usb_phy_power(true);
120
121	if (ret)
122		return ret;
123
124	pm_runtime_enable(&pdev->dev);
125	pm_runtime_get_sync(&pdev->dev);
126
127	return 0;
128}
129
130static void usb_power_off(struct platform_device *pdev)
131{
132	if (r8a7778_usb_phy_power(false))
133		return;
134
135	pm_runtime_put_sync(&pdev->dev);
136	pm_runtime_disable(&pdev->dev);
137}
138
139static int ehci_init_internal_buffer(struct usb_hcd *hcd)
140{
141	/*
142	 * Below are recommended values from the datasheet;
143	 * see [USB :: Setting of EHCI Internal Buffer].
144	 */
145	/* EHCI IP internal buffer setting */
146	iowrite32(0x00ff0040, hcd->regs + 0x0094);
147	/* EHCI IP internal buffer enable */
148	iowrite32(0x00000001, hcd->regs + 0x009C);
149
150	return 0;
151}
152
153static struct usb_ehci_pdata ehci_pdata __initdata = {
154	.power_on	= usb_power_on,
155	.power_off	= usb_power_off,
156	.power_suspend	= usb_power_off,
157	.pre_setup	= ehci_init_internal_buffer,
158};
159
160static struct resource ehci_resources[] __initdata = {
161	DEFINE_RES_MEM(0xffe70000, 0x400),
162	DEFINE_RES_IRQ(gic_iid(0x4c)),
163};
164
165static struct usb_ohci_pdata ohci_pdata __initdata = {
166	.power_on	= usb_power_on,
167	.power_off	= usb_power_off,
168	.power_suspend	= usb_power_off,
169};
170
171static struct resource ohci_resources[] __initdata = {
172	DEFINE_RES_MEM(0xffe70400, 0x400),
173	DEFINE_RES_IRQ(gic_iid(0x4c)),
174};
175
176#define USB_PLATFORM_INFO(hci)					\
177static struct platform_device_info hci##_info __initdata = {	\
178	.name		= #hci "-platform",			\
179	.id		= -1,					\
180	.res		= hci##_resources,			\
181	.num_res	= ARRAY_SIZE(hci##_resources),		\
182	.data		= &hci##_pdata,				\
183	.size_data	= sizeof(hci##_pdata),			\
184	.dma_mask	= DMA_BIT_MASK(32),			\
185}
186
187USB_PLATFORM_INFO(ehci);
188USB_PLATFORM_INFO(ohci);
189
190/* PFC/GPIO */
191static struct resource pfc_resources[] __initdata = {
192	DEFINE_RES_MEM(0xfffc0000, 0x118),
193};
194
195#define R8A7778_GPIO(idx)						\
196static struct resource r8a7778_gpio##idx##_resources[] __initdata = {	\
197	DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),		\
198	DEFINE_RES_IRQ(gic_iid(0x87)),					\
199};									\
200									\
201static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
202	.gpio_base	= 32 * (idx),					\
203	.irq_base	= GPIO_IRQ_BASE(idx),				\
204	.number_of_pins	= 32,						\
205	.pctl_name	= "pfc-r8a7778",				\
206}
207
208R8A7778_GPIO(0);
209R8A7778_GPIO(1);
210R8A7778_GPIO(2);
211R8A7778_GPIO(3);
212R8A7778_GPIO(4);
213
214#define r8a7778_register_gpio(idx)				\
215	platform_device_register_resndata(			\
216		NULL, "gpio_rcar", idx,				\
217		r8a7778_gpio##idx##_resources,			\
218		ARRAY_SIZE(r8a7778_gpio##idx##_resources),	\
219		&r8a7778_gpio##idx##_platform_data,		\
220		sizeof(r8a7778_gpio##idx##_platform_data))
221
222void __init r8a7778_pinmux_init(void)
223{
224	platform_device_register_simple(
225		"pfc-r8a7778", -1,
226		pfc_resources,
227		ARRAY_SIZE(pfc_resources));
228
229	r8a7778_register_gpio(0);
230	r8a7778_register_gpio(1);
231	r8a7778_register_gpio(2);
232	r8a7778_register_gpio(3);
233	r8a7778_register_gpio(4);
234};
235
236/* I2C */
237static struct resource i2c_resources[] __initdata = {
238	/* I2C0 */
239	DEFINE_RES_MEM(0xffc70000, 0x1000),
240	DEFINE_RES_IRQ(gic_iid(0x63)),
241	/* I2C1 */
242	DEFINE_RES_MEM(0xffc71000, 0x1000),
243	DEFINE_RES_IRQ(gic_iid(0x6e)),
244	/* I2C2 */
245	DEFINE_RES_MEM(0xffc72000, 0x1000),
246	DEFINE_RES_IRQ(gic_iid(0x6c)),
247	/* I2C3 */
248	DEFINE_RES_MEM(0xffc73000, 0x1000),
249	DEFINE_RES_IRQ(gic_iid(0x6d)),
250};
251
252static void __init r8a7778_register_i2c(int id)
253{
254	BUG_ON(id < 0 || id > 3);
255
256	platform_device_register_simple(
257		"i2c-rcar", id,
258		i2c_resources + (2 * id), 2);
259}
260
261/* HSPI */
262static struct resource hspi_resources[] __initdata = {
263	/* HSPI0 */
264	DEFINE_RES_MEM(0xfffc7000, 0x18),
265	DEFINE_RES_IRQ(gic_iid(0x5f)),
266	/* HSPI1 */
267	DEFINE_RES_MEM(0xfffc8000, 0x18),
268	DEFINE_RES_IRQ(gic_iid(0x74)),
269	/* HSPI2 */
270	DEFINE_RES_MEM(0xfffc6000, 0x18),
271	DEFINE_RES_IRQ(gic_iid(0x75)),
272};
273
274static void __init r8a7778_register_hspi(int id)
275{
276	BUG_ON(id < 0 || id > 2);
277
278	platform_device_register_simple(
279		"sh-hspi", id,
280		hspi_resources + (2 * id), 2);
281}
282
283void __init r8a7778_add_dt_devices(void)
284{
285#ifdef CONFIG_CACHE_L2X0
286	void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
287	if (base) {
288		/*
289		 * Shared attribute override enable, 64K*16way
290		 * don't call iounmap(base)
291		 */
292		l2x0_init(base, 0x00400000, 0xc20f0fff);
293	}
294#endif
295
296	r8a7778_register_tmu(0);
297}
298
299/* HPB-DMA */
300
301/* Asynchronous mode register (ASYNCMDR) bits */
302#define HPB_DMAE_ASYNCMDR_ASMD22_MASK	BIT(2)	/* SDHI0 */
303#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE	BIT(2)	/* SDHI0 */
304#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI	0	/* SDHI0 */
305#define HPB_DMAE_ASYNCMDR_ASMD21_MASK	BIT(1)	/* SDHI0 */
306#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE	BIT(1)	/* SDHI0 */
307#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI	0	/* SDHI0 */
308
309#define HPBDMA_SSI(_id)				\
310{						\
311	.id	= HPBDMA_SLAVE_SSI## _id ##_TX,	\
312	.addr	= 0xffd91008 + (_id * 0x40),	\
313	.dcr	= HPB_DMAE_DCR_CT |		\
314		  HPB_DMAE_DCR_DIP |		\
315		  HPB_DMAE_DCR_SPDS_32BIT |	\
316		  HPB_DMAE_DCR_DMDL |		\
317		  HPB_DMAE_DCR_DPDS_32BIT,	\
318	.port   = _id + (_id << 8),		\
319	.dma_ch = (28 + _id),			\
320}, {						\
321	.id	= HPBDMA_SLAVE_SSI## _id ##_RX,	\
322	.addr	= 0xffd9100c + (_id * 0x40),	\
323	.dcr	= HPB_DMAE_DCR_CT |		\
324		  HPB_DMAE_DCR_DIP |		\
325		  HPB_DMAE_DCR_SMDL |		\
326		  HPB_DMAE_DCR_SPDS_32BIT |	\
327		  HPB_DMAE_DCR_DPDS_32BIT,	\
328	.port   = _id + (_id << 8),		\
329	.dma_ch = (28 + _id),			\
330}
331
332#define HPBDMA_HPBIF(_id)				\
333{							\
334	.id	= HPBDMA_SLAVE_HPBIF## _id ##_TX,	\
335	.addr	= 0xffda0000 + (_id * 0x1000),		\
336	.dcr	= HPB_DMAE_DCR_CT |			\
337		  HPB_DMAE_DCR_DIP |			\
338		  HPB_DMAE_DCR_SPDS_32BIT |		\
339		  HPB_DMAE_DCR_DMDL |			\
340		  HPB_DMAE_DCR_DPDS_32BIT,		\
341	.port   = 0x1111,				\
342	.dma_ch = (28 + _id),				\
343}, {							\
344	.id	= HPBDMA_SLAVE_HPBIF## _id ##_RX,	\
345	.addr	= 0xffda0000 + (_id * 0x1000),		\
346	.dcr	= HPB_DMAE_DCR_CT |			\
347		  HPB_DMAE_DCR_DIP |			\
348		  HPB_DMAE_DCR_SMDL |			\
349		  HPB_DMAE_DCR_SPDS_32BIT |		\
350		  HPB_DMAE_DCR_DPDS_32BIT,		\
351	.port   = 0x1111,				\
352	.dma_ch = (28 + _id),				\
353}
354
355static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
356	{
357		.id	= HPBDMA_SLAVE_SDHI0_TX,
358		.addr	= 0xffe4c000 + 0x30,
359		.dcr	= HPB_DMAE_DCR_SPDS_16BIT |
360			  HPB_DMAE_DCR_DMDL |
361			  HPB_DMAE_DCR_DPDS_16BIT,
362		.rstr	= HPB_DMAE_ASYNCRSTR_ASRST21 |
363			  HPB_DMAE_ASYNCRSTR_ASRST22 |
364			  HPB_DMAE_ASYNCRSTR_ASRST23,
365		.mdr	= HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
366		.mdm	= HPB_DMAE_ASYNCMDR_ASMD21_MASK,
367		.port	= 0x0D0C,
368		.flags	= HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
369		.dma_ch	= 21,
370	}, {
371		.id	= HPBDMA_SLAVE_SDHI0_RX,
372		.addr	= 0xffe4c000 + 0x30,
373		.dcr	= HPB_DMAE_DCR_SMDL |
374			  HPB_DMAE_DCR_SPDS_16BIT |
375			  HPB_DMAE_DCR_DPDS_16BIT,
376		.rstr	= HPB_DMAE_ASYNCRSTR_ASRST21 |
377			  HPB_DMAE_ASYNCRSTR_ASRST22 |
378			  HPB_DMAE_ASYNCRSTR_ASRST23,
379		.mdr	= HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
380		.mdm	= HPB_DMAE_ASYNCMDR_ASMD22_MASK,
381		.port	= 0x0D0C,
382		.flags	= HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
383		.dma_ch	= 22,
384	}, {
385		.id	= HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
386		.addr	= 0xffe60018,
387		.dcr	= HPB_DMAE_DCR_SPDS_32BIT |
388			  HPB_DMAE_DCR_DMDL |
389			  HPB_DMAE_DCR_DPDS_32BIT,
390		.port	= 0x0000,
391		.dma_ch	= 14,
392	}, {
393		.id	= HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
394		.addr	= 0xffe6001c,
395		.dcr	= HPB_DMAE_DCR_SMDL |
396			  HPB_DMAE_DCR_SPDS_32BIT |
397			  HPB_DMAE_DCR_DPDS_32BIT,
398		.port	= 0x0101,
399		.dma_ch	= 15,
400	},
401
402	HPBDMA_SSI(0),
403	HPBDMA_SSI(1),
404	HPBDMA_SSI(2),
405	HPBDMA_SSI(3),
406	HPBDMA_SSI(4),
407	HPBDMA_SSI(5),
408	HPBDMA_SSI(6),
409	HPBDMA_SSI(7),
410	HPBDMA_SSI(8),
411
412	HPBDMA_HPBIF(0),
413	HPBDMA_HPBIF(1),
414	HPBDMA_HPBIF(2),
415	HPBDMA_HPBIF(3),
416	HPBDMA_HPBIF(4),
417	HPBDMA_HPBIF(5),
418	HPBDMA_HPBIF(6),
419	HPBDMA_HPBIF(7),
420	HPBDMA_HPBIF(8),
421};
422
423static const struct hpb_dmae_channel hpb_dmae_channels[] = {
424	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
425	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
426	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
427	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
428	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX),   /* ch. 28 */
429	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX),   /* ch. 28 */
430	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
431	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
432	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX),   /* ch. 29 */
433	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX),   /* ch. 29 */
434	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
435	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
436	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX),   /* ch. 30 */
437	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX),   /* ch. 30 */
438	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
439	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
440	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX),   /* ch. 31 */
441	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX),   /* ch. 31 */
442	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
443	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
444	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX),   /* ch. 32 */
445	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX),   /* ch. 32 */
446	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
447	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
448	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX),   /* ch. 33 */
449	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX),   /* ch. 33 */
450	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
451	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
452	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX),   /* ch. 34 */
453	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX),   /* ch. 34 */
454	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
455	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
456	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX),   /* ch. 35 */
457	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX),   /* ch. 35 */
458	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
459	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
460	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX),   /* ch. 36 */
461	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX),   /* ch. 36 */
462	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
463	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
464};
465
466static struct hpb_dmae_pdata dma_platform_data __initdata = {
467	.slaves			= hpb_dmae_slaves,
468	.num_slaves		= ARRAY_SIZE(hpb_dmae_slaves),
469	.channels		= hpb_dmae_channels,
470	.num_channels		= ARRAY_SIZE(hpb_dmae_channels),
471	.ts_shift		= {
472		[XMIT_SZ_8BIT]	= 0,
473		[XMIT_SZ_16BIT]	= 1,
474		[XMIT_SZ_32BIT]	= 2,
475	},
476	.num_hw_channels	= 39,
477};
478
479static struct resource hpb_dmae_resources[] __initdata = {
480	/* Channel registers */
481	DEFINE_RES_MEM(0xffc08000, 0x1000),
482	/* Common registers */
483	DEFINE_RES_MEM(0xffc09000, 0x170),
484	/* Asynchronous reset registers */
485	DEFINE_RES_MEM(0xffc00300, 4),
486	/* Asynchronous mode registers */
487	DEFINE_RES_MEM(0xffc00400, 4),
488	/* IRQ for DMA channels */
489	DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
490};
491
492static void __init r8a7778_register_hpb_dmae(void)
493{
494	platform_device_register_resndata(NULL, "hpb-dma-engine",
495					  -1, hpb_dmae_resources,
496					  ARRAY_SIZE(hpb_dmae_resources),
497					  &dma_platform_data,
498					  sizeof(dma_platform_data));
499}
500
501void __init r8a7778_add_standard_devices(void)
502{
503	r8a7778_add_dt_devices();
504	r8a7778_register_scif(0);
505	r8a7778_register_scif(1);
506	r8a7778_register_scif(2);
507	r8a7778_register_scif(3);
508	r8a7778_register_scif(4);
509	r8a7778_register_scif(5);
510	r8a7778_register_i2c(0);
511	r8a7778_register_i2c(1);
512	r8a7778_register_i2c(2);
513	r8a7778_register_i2c(3);
514	r8a7778_register_hspi(0);
515	r8a7778_register_hspi(1);
516	r8a7778_register_hspi(2);
517
518	r8a7778_register_hpb_dmae();
519}
520
521void __init r8a7778_init_late(void)
522{
523	shmobile_init_late();
524	platform_device_register_full(&ehci_info);
525	platform_device_register_full(&ohci_info);
526}
527
528static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
529	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
530	.sense_bitfield_width = 2,
531};
532
533static struct resource irqpin_resources[] __initdata = {
534	DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
535	DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
536	DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
537	DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
538	DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
539	DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
540	DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
541	DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
542	DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
543};
544
545void __init r8a7778_init_irq_extpin_dt(int irlm)
546{
547	void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
548	unsigned long tmp;
549
550	if (!icr0) {
551		pr_warn("r8a7778: unable to setup external irq pin mode\n");
552		return;
553	}
554
555	tmp = ioread32(icr0);
556	if (irlm)
557		tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
558	else
559		tmp &= ~(1 << 23); /* IRL mode - not supported */
560	tmp |= (1 << 21); /* LVLMODE = 1 */
561	iowrite32(tmp, icr0);
562	iounmap(icr0);
563}
564
565void __init r8a7778_init_irq_extpin(int irlm)
566{
567	r8a7778_init_irq_extpin_dt(irlm);
568	if (irlm)
569		platform_device_register_resndata(
570			NULL, "renesas_intc_irqpin", -1,
571			irqpin_resources, ARRAY_SIZE(irqpin_resources),
572			&irqpin_platform_data, sizeof(irqpin_platform_data));
573}
574
575void __init r8a7778_init_delay(void)
576{
577	shmobile_init_delay();
578}
579
580#ifdef CONFIG_USE_OF
581#define INT2SMSKCR0	0x82288 /* 0xfe782288 */
582#define INT2SMSKCR1	0x8228c /* 0xfe78228c */
583
584#define INT2NTSR0	0x00018 /* 0xfe700018 */
585#define INT2NTSR1	0x0002c /* 0xfe70002c */
586void __init r8a7778_init_irq_dt(void)
587{
588	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
589
590	BUG_ON(!base);
591
592	irqchip_init();
593
594	/* route all interrupts to ARM */
595	__raw_writel(0x73ffffff, base + INT2NTSR0);
596	__raw_writel(0xffffffff, base + INT2NTSR1);
597
598	/* unmask all known interrupts in INTCS2 */
599	__raw_writel(0x08330773, base + INT2SMSKCR0);
600	__raw_writel(0x00311110, base + INT2SMSKCR1);
601
602	iounmap(base);
603}
604
605static const char *r8a7778_compat_dt[] __initdata = {
606	"renesas,r8a7778",
607	NULL,
608};
609
610DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
611	.init_early	= r8a7778_init_delay,
612	.init_irq	= r8a7778_init_irq_dt,
613	.init_late	= shmobile_init_late,
614	.dt_compat	= r8a7778_compat_dt,
615MACHINE_END
616
617#endif /* CONFIG_USE_OF */
618