1/*
2 * arch/arm/mach-tegra/flowctrl.h
3 *
4 * functions and macros to control the flowcontroller
5 *
6 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __MACH_TEGRA_FLOWCTRL_H
22#define __MACH_TEGRA_FLOWCTRL_H
23
24#define FLOW_CTRL_HALT_CPU0_EVENTS	0x0
25#define FLOW_CTRL_WAITEVENT		(2 << 29)
26#define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
27#define FLOW_CTRL_JTAG_RESUME		(1 << 28)
28#define FLOW_CTRL_SCLK_RESUME		(1 << 27)
29#define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
30#define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
31#define FLOW_CTRL_HALT_LIC_IRQ		(1 << 11)
32#define FLOW_CTRL_HALT_LIC_FIQ		(1 << 10)
33#define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
34#define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
35#define FLOW_CTRL_CPU0_CSR		0x8
36#define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
37#define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
38#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL	(1 << 13)
39#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU	(1 << 12)
40#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
41		FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
42		FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
43#define FLOW_CTRL_CSR_ENABLE		(1 << 0)
44#define FLOW_CTRL_HALT_CPU1_EVENTS	0x14
45#define FLOW_CTRL_CPU1_CSR		0x18
46
47#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)
48#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)
49#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP	0
50
51#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0		(1 << 8)
52#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP	(0xF << 4)
53#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP	(0xF << 8)
54
55#ifndef __ASSEMBLY__
56u32 flowctrl_read_cpu_csr(unsigned int cpuid);
57void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
58void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
59
60void flowctrl_cpu_suspend_enter(unsigned int cpuid);
61void flowctrl_cpu_suspend_exit(unsigned int cpuid);
62
63void tegra_flowctrl_init(void);
64#endif
65
66#endif
67