1/* 2 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 3 * Tomasz Figa <t.figa@samsung.com> 4 * Copyright (C) 2008 Openmoko, Inc. 5 * Copyright (C) 2004-2008 Simtec Electronics 6 * Ben Dooks <ben@simtec.co.uk> 7 * http://armlinux.simtec.co.uk/ 8 * 9 * Samsung common power management (suspend to RAM) debug support 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include <linux/serial_core.h> 17#include <linux/serial_s3c.h> 18#include <linux/io.h> 19 20#include <asm/mach/map.h> 21 22#include <plat/cpu.h> 23#include <plat/pm-common.h> 24 25#ifdef CONFIG_SAMSUNG_ATAGS 26#include <mach/pm-core.h> 27#else 28static inline void s3c_pm_debug_init_uart(void) {} 29static inline void s3c_pm_arch_update_uart(void __iomem *regs, 30 struct pm_uart_save *save) {} 31#endif 32 33static struct pm_uart_save uart_save; 34 35extern void printascii(const char *); 36 37void s3c_pm_dbg(const char *fmt, ...) 38{ 39 va_list va; 40 char buff[256]; 41 42 va_start(va, fmt); 43 vsnprintf(buff, sizeof(buff), fmt, va); 44 va_end(va); 45 46 printascii(buff); 47} 48 49void s3c_pm_debug_init(void) 50{ 51 /* restart uart clocks so we can use them to output */ 52 s3c_pm_debug_init_uart(); 53} 54 55static inline void __iomem *s3c_pm_uart_base(void) 56{ 57 unsigned long paddr; 58 unsigned long vaddr; 59 60 debug_ll_addr(&paddr, &vaddr); 61 62 return (void __iomem *)vaddr; 63} 64 65void s3c_pm_save_uarts(void) 66{ 67 void __iomem *regs = s3c_pm_uart_base(); 68 struct pm_uart_save *save = &uart_save; 69 70 save->ulcon = __raw_readl(regs + S3C2410_ULCON); 71 save->ucon = __raw_readl(regs + S3C2410_UCON); 72 save->ufcon = __raw_readl(regs + S3C2410_UFCON); 73 save->umcon = __raw_readl(regs + S3C2410_UMCON); 74 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); 75 76 if (!soc_is_s3c2410()) 77 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); 78 79 S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", 80 regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); 81} 82 83void s3c_pm_restore_uarts(void) 84{ 85 void __iomem *regs = s3c_pm_uart_base(); 86 struct pm_uart_save *save = &uart_save; 87 88 s3c_pm_arch_update_uart(regs, save); 89 90 __raw_writel(save->ulcon, regs + S3C2410_ULCON); 91 __raw_writel(save->ucon, regs + S3C2410_UCON); 92 __raw_writel(save->ufcon, regs + S3C2410_UFCON); 93 __raw_writel(save->umcon, regs + S3C2410_UMCON); 94 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); 95 96 if (!soc_is_s3c2410()) 97 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); 98} 99