ptrace.h revision 7606c37d4a447ea3b0efb2165d3ccf516b7d8696 
1/*
2 * Based on arch/arm/include/asm/ptrace.h
3 *
4 * Copyright (C) 1996-2003 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_PTRACE_H
20#define __ASM_PTRACE_H
21
22#include <linux/types.h>
23
24#include <asm/hwcap.h>
25
26#ifdef __KERNEL__
27/* AArch32-specific ptrace requests */
28#define COMPAT_PTRACE_GETREGS		12
29#define COMPAT_PTRACE_SETREGS		13
30#define COMPAT_PTRACE_GET_THREAD_AREA	22
31#define COMPAT_PTRACE_SET_SYSCALL	23
32#define COMPAT_PTRACE_GETVFPREGS	27
33#define COMPAT_PTRACE_SETVFPREGS	28
34#define COMPAT_PTRACE_GETHBPREGS	29
35#define COMPAT_PTRACE_SETHBPREGS	30
36#endif
37
38/*
39 * PSR bits
40 */
41#define PSR_MODE_EL0t	0x00000000
42#define PSR_MODE_EL1t	0x00000004
43#define PSR_MODE_EL1h	0x00000005
44#define PSR_MODE_EL2t	0x00000008
45#define PSR_MODE_EL2h	0x00000009
46#define PSR_MODE_EL3t	0x0000000c
47#define PSR_MODE_EL3h	0x0000000d
48#define PSR_MODE_MASK	0x0000000f
49
50/* AArch32 CPSR bits */
51#define PSR_MODE32_BIT		0x00000010
52#ifdef __KERNEL__
53#define COMPAT_PSR_MODE_USR	0x00000010
54#define COMPAT_PSR_T_BIT	0x00000020
55#define COMPAT_PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
56#endif
57
58/* AArch64 SPSR bits */
59#define PSR_F_BIT	0x00000040
60#define PSR_I_BIT	0x00000080
61#define PSR_A_BIT	0x00000100
62#define PSR_D_BIT	0x00000200
63#define PSR_Q_BIT	0x08000000
64#define PSR_V_BIT	0x10000000
65#define PSR_C_BIT	0x20000000
66#define PSR_Z_BIT	0x40000000
67#define PSR_N_BIT	0x80000000
68
69/*
70 * Groups of PSR bits
71 */
72#define PSR_f		0xff000000	/* Flags		*/
73#define PSR_s		0x00ff0000	/* Status		*/
74#define PSR_x		0x0000ff00	/* Extension		*/
75#define PSR_c		0x000000ff	/* Control		*/
76
77#ifdef __KERNEL__
78/*
79 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
80 * process is located in memory.
81 */
82#define COMPAT_PT_TEXT_ADDR		0x10000
83#define COMPAT_PT_DATA_ADDR		0x10004
84#define COMPAT_PT_TEXT_END_ADDR		0x10008
85#endif
86
87#ifndef __ASSEMBLY__
88
89/*
90 * User structures for general purpose, floating point and debug registers.
91 */
92struct user_pt_regs {
93	__u64		regs[31];
94	__u64		sp;
95	__u64		pc;
96	__u64		pstate;
97};
98
99struct user_fpsimd_state {
100	__uint128_t	vregs[32];
101	__u32		fpsr;
102	__u32		fpcr;
103};
104
105struct user_hwdebug_state {
106	__u32		dbg_info;
107	struct {
108		__u64	addr;
109		__u32	ctrl;
110	}		dbg_regs[16];
111};
112
113#ifdef __KERNEL__
114
115/* sizeof(struct user) for AArch32 */
116#define COMPAT_USER_SZ	296
117/* AArch32 uses x13 as the stack pointer... */
118#define compat_sp	regs[13]
119/* ... and x14 as the link register. */
120#define compat_lr	regs[14]
121
122/*
123 * This struct defines the way the registers are stored on the stack during an
124 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
125 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
126 */
127struct pt_regs {
128	union {
129		struct user_pt_regs user_regs;
130		struct {
131			u64 regs[31];
132			u64 sp;
133			u64 pc;
134			u64 pstate;
135		};
136	};
137	u64 orig_x0;
138	u64 syscallno;
139};
140
141#define arch_has_single_step()	(1)
142
143#ifdef CONFIG_COMPAT
144#define compat_thumb_mode(regs) \
145	(((regs)->pstate & COMPAT_PSR_T_BIT))
146#else
147#define compat_thumb_mode(regs) (0)
148#endif
149
150#define user_mode(regs)	\
151	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
152
153#define compat_user_mode(regs)	\
154	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
155	 (PSR_MODE32_BIT | PSR_MODE_EL0t))
156
157#define processor_mode(regs) \
158	((regs)->pstate & PSR_MODE_MASK)
159
160#define interrupts_enabled(regs) \
161	(!((regs)->pstate & PSR_I_BIT))
162
163#define fast_interrupts_enabled(regs) \
164	(!((regs)->pstate & PSR_F_BIT))
165
166#define user_stack_pointer(regs) \
167	((regs)->sp)
168
169/*
170 * Are the current registers suitable for user mode? (used to maintain
171 * security in signal handlers)
172 */
173static inline int valid_user_regs(struct user_pt_regs *regs)
174{
175	if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
176		regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
177
178		/* The T bit is reserved for AArch64 */
179		if (!(regs->pstate & PSR_MODE32_BIT))
180			regs->pstate &= ~COMPAT_PSR_T_BIT;
181
182		return 1;
183	}
184
185	/*
186	 * Force PSR to something logical...
187	 */
188	regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
189			COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
190
191	if (!(regs->pstate & PSR_MODE32_BIT)) {
192		regs->pstate &= ~COMPAT_PSR_T_BIT;
193		regs->pstate |= PSR_MODE_EL0t;
194	}
195
196	return 0;
197}
198
199#define instruction_pointer(regs)	(regs)->pc
200
201#ifdef CONFIG_SMP
202extern unsigned long profile_pc(struct pt_regs *regs);
203#else
204#define profile_pc(regs) instruction_pointer(regs)
205#endif
206
207extern int aarch32_break_trap(struct pt_regs *regs);
208
209#endif /* __KERNEL__ */
210
211#endif /* __ASSEMBLY__ */
212
213#endif
214