| b2e7986f0eb37626a14d89682d61ed0eb68a5a01 |
|
22-Apr-2015 |
Daniel Kurtz <djkurtz@google.com> |
Revert "arm64: ptrace: allow tracer to skip a system call"
This reverts commit f459f3db45c06394d3213ee5fa28f2f90326ce15.
To be replaced with arm64 seccomp from mainline v3.19.
Signed-off-by: Daniel Kurtz <djkurtz@google.com>
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| 9d2c178aa066efe10b4f421c347583f059dca3cc |
|
22-Apr-2015 |
Daniel Kurtz <djkurtz@google.com> |
Revert "arm64: add seccomp support"
This reverts commit 923b5e258a9a30ccf8ce133c63f15b21da2182d6.
[djkurtz: trivial conflict fixup in arch/arm64/Kconfig]
To be replaced with arm64 seccomp from mainline v3.19.
Change-Id: Icad82d42b1b3d755c8130657cc3675d460320b86
Signed-off-by: Daniel Kurtz <djkurtz@google.com>
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| 7540dadaf9a8b0f67d41f8bc216ca4d67d9128b0 |
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21-Jan-2015 |
Suzuki K. Poulose <suzuki.poulose@arm.com> |
arm64: Emulate SETEND for AArch32 tasks
Emulate deprecated 'setend' instruction for AArch32 bit tasks.
setend [le/be] - Sets the endianness of EL0
On systems with CPUs which support mixed endian at EL0, the hardware
support for the instruction can be enabled by setting the SCTLR_EL1.SED
bit. Like the other emulated instructions it is controlled by an entry in
/proc/sys/abi/. For more information see :
Documentation/arm64/legacy_instructions.txt
The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which
will be reflected in the PSTATE.E in AArch32 context.
This patch also restores the native endianness for the execution of signal
handlers, since the process could have changed the endianness.
Note: All CPUs on the system must have mixed endian support at EL0. Once the
handler is registered, hotplugging a CPU which doesn't support mixed endian,
could lead to unexpected results/behavior in applications.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I5993237889a049a23f6c234daa130d3a740d5525
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| 9e7934bb27b71f4bd99ce5074e494731ab403ff9 |
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06-Feb-2015 |
Ruchi Kandoi <kandoiruchi@google.com> |
Revert "arm64: ptrace: add is_wide_instruction() macro"
This reverts commit 6fdf4dcc8cd7969bbf0cd56a6d18d03acfc10387.
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| 923b5e258a9a30ccf8ce133c63f15b21da2182d6 |
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04-Sep-2014 |
AKASHI Takahiro <takahiro.akashi@linaro.org> |
arm64: add seccomp support
Note: This patch is from v6 of Takahiro's proposed
"arm64: add seccomp support" patchset (leecam@google.com)
secure_computing() is called first in syscall_trace_enter() so that a system
call will be aborted quickly without doing succeeding syscall tracing,
contrary to other cases, if seccomp rules deny that system call.
On compat task, syscall numbers for system calls allowed in seccomp mode 1
are different from those on normal tasks, and so _NR_seccomp_xxx_32's need
to be redefined.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Conflicts:
arch/arm64/Kconfig
arch/arm64/kernel/entry.S
Change-Id: I5ec44507d7e536df7ec9d62d30a418c26ef15100
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| f459f3db45c06394d3213ee5fa28f2f90326ce15 |
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04-Sep-2014 |
AKASHI Takahiro <takahiro.akashi@linaro.org> |
arm64: ptrace: allow tracer to skip a system call
Note: This patch is from v6 of Takahiro's proposed
"arm64: add seccomp support" patchset (leecam@google.com)
If tracer specifies -1 as a syscall number, this traced system call should
be skipped with a value in x0 used as a return value.
This patch enables this semantics, but there is a restriction here:
when syscall(-1) is issued by user, tracer cannot skip this system call
and modify a return value at syscall entry.
In order to ease this flavor, we need to treat whatever value in x0 as
a return value, but this might result in a bogus value being returned,
especially when tracer doesn't do anything at this syscall.
So we always return ENOSYS instead, while we have another chance to change
a return value at syscall exit.
Please also note:
* syscall entry tracing and syscall exit tracing (ftrace tracepoint and
audit) are always executed, if enabled, even when skipping a system call
(that is, -1).
In this way, we can avoid a potential bug where audit_syscall_entry()
might be called without audit_syscall_exit() at the previous system call
being called, that would cause OOPs in audit_syscall_entry().
* syscallno may also be set to -1 if a fatal signal (SIGKILL) is detected
in tracehook_report_syscall_entry(), but since a value set to x0 (ENOSYS)
is not used in this case, we may neglect the case.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Conflicts:
arch/arm64/kernel/entry.S
Change-Id: Ifcdcdbcb7c8cf97e5b5f1086a1ea4107e1d4f9a8
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| 6fdf4dcc8cd7969bbf0cd56a6d18d03acfc10387 |
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29-Jan-2014 |
Alex Van Brunt <avanbrunt@nvidia.com> |
arm64: ptrace: add is_wide_instruction() macro
Add the is_wide_instruction() macro. This was copied from the arm
architecture.
Change-Id: I28f83b47f5c587fe778dc2846df77673f8dd918b
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/361737
Reviewed-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/365060
Reviewed-by: Richard Wiley <rwiley@nvidia.com>
Tested-by: Oskari Jaaskelainen <oskarij@nvidia.com>
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| 2520d039728b2a3c5ae7f79fe2a0e9d182855b12 |
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29-Aug-2014 |
Catalin Marinas <catalin.marinas@arm.com> |
arm64: Add brackets around user_stack_pointer()
Commit 5f888a1d33 (ARM64: perf: support dwarf unwinding in compat mode)
changes user_stack_pointer() to return the compat SP for 32-bit tasks
but without brackets around the whole definition, with possible issues
on the call sites (noticed with a subsequent fix for KSTK_ESP).
Fixes: 5f888a1d33c4 (ARM64: perf: support dwarf unwinding in compat mode)
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 974c8e450b9327a03453a4a450a2030b1bd42b5f |
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06-Jun-2014 |
Marc Zyngier <marc.zyngier@arm.com> |
arm64: fix el2_setup check of CurrentEL
The CurrentEL system register reports the Current Exception Level
of the CPU. It doesn't say anything about the stack handling, and
yet we compare it to PSR_MODE_EL2t and PSR_MODE_EL2h.
It works by chance because PSR_MODE_EL2t happens to match the right
bits, but that's otherwise a very bad idea. Just check for the EL
value instead.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[catalin.marinas@arm.com: fixed arch/arm64/kernel/efi-entry.S]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| d34a3ebd8d25cf691a94fae66a957a480cf46430 |
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30-Apr-2014 |
AKASHI Takahiro <takahiro.akashi@linaro.org> |
arm64: Add regs_return_value() in syscall.h
This macro, regs_return_value, is used mainly for audit to record system
call's results, but may also be used in test_kprobes.c.
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Richard Guy Briggs <rgb@redhat.com>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 5f888a1d33c48900012e6b4c18296ce7c715dc6c |
|
03-Feb-2014 |
Jean Pihet <jean.pihet@linaro.org> |
ARM64: perf: support dwarf unwinding in compat mode
Add support for unwinding using the dwarf information in compat
mode. Using the correct user stack pointer allows perf to record
the frames correctly in the native and compat modes.
Note that although the dwarf frame unwinding works ok using
libunwind in native mode (on ARMv7 & ARMv8), some changes are
required to the libunwind code for the compat mode. Those changes
are posted separately on the libunwind mailing list.
Tested on ARMv8 platform with v8 and compat v7 binaries, the latter
are statically built.
Signed-off-by: Jean Pihet <jean.pihet@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 2ee0d7fd36a3f87bc5b29b1ec54ad6728deedb41 |
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03-Feb-2014 |
Jean Pihet <jean.pihet@linaro.org> |
ARM64: perf: add support for perf registers API
This patch implements the functions required for the perf registers API,
allowing the perf tool to interface kernel register dumps with libunwind
in order to provide userspace backtracing.
Compat mode is also supported.
Only the general purpose user space registers are exported, i.e.:
PERF_REG_ARM_X0,
...
PERF_REG_ARM_X28,
PERF_REG_ARM_FP,
PERF_REG_ARM_LR,
PERF_REG_ARM_SP,
PERF_REG_ARM_PC
and not the PERF_REG_ARM_V* registers.
Signed-off-by: Jean Pihet <jean.pihet@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 58dcc204f18af2821f683b235bb376f9db2557f5 |
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28-Jan-2014 |
Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> |
misc: debug: remove compilation warnings
typecast instruction_pointer macro to unsigned long to
resolve following compiler warnings like
warning: format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'u64' [-Wformat]
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| a795a38eb91cf72c4a05e72a9c84e317ee179a48 |
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11-Oct-2013 |
Will Deacon <will.deacon@arm.com> |
arm64: compat: add support for big-endian (BE8) AArch32 binaries
This patch adds support for BE8 AArch32 tasks to the compat layer.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 1442b6ed249d2b3d2cfcf45b65ac64393495c96c |
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16-Mar-2013 |
Will Deacon <will.deacon@arm.com> |
arm64: debug: consolidate software breakpoint handlers
The software breakpoint handlers are hooked in directly from ptrace,
which makes it difficult to add additional handlers for things like
kprobes and kgdb.
This patch moves the handling code into debug-monitors.c, where we can
dispatch to different debug subsystems more easily.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 10a3cc2f764038e388d6fc3510142ae7d23fb2d9 |
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23-Jan-2013 |
Marc Zyngier <Marc.Zyngier@arm.com> |
arm64: add COMPAT_PSR_*_BIT flags
In order to mess with the processor state when running 32bit
guests, define all the AArch32 PSR flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 9ec218b8f5a22bf909b8c016b2abd75763f94acb |
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04-Oct-2012 |
Marc Zyngier <marc.zyngier@arm.com> |
arm64: add AArch32 execution modes to ptrace.h
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 88483ec647c314dedbe157e567c3d24c683cc90f |
|
03-Oct-2012 |
Marc Zyngier <marc.zyngier@arm.com> |
arm64: expand register mapping between AArch32 and AArch64
The general purpose registers in AArch32 are mapped in an
architecturally defined manner into the AArch64 registers.
It allows the AArch32 registers of an application or a virtual
machine to be inspected by the OS or an hypervisor.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 4262a727621ceadfb38cb90a69804b6ee6be746e |
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11-Oct-2012 |
David Howells <dhowells@redhat.com> |
UAPI: (Scripted) Disintegrate arch/arm64/include/asm
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Michael Kerrisk <mtk.manpages@gmail.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Dave Jones <davej@redhat.com>
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| 7606c37d4a447ea3b0efb2165d3ccf516b7d8696 |
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10-Oct-2012 |
Catalin Marinas <catalin.marinas@arm.com> |
arm64: Do not export the compat-specific definitions to the user
This patch adds #ifdef __KERNEL__ guards around the COMPAT_* definitions
to avoid exporting them to user. AArch32 user requiring the kernel
headers must use those generated with ARCH=arm.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
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| 27aa55c5e5123fa8b8ad0156559d34d7edff58ca |
|
27-Sep-2012 |
Will Deacon <will.deacon@arm.com> |
arm64: ptrace: remove obsolete ptrace request numbers from user headers
The use of regsets has removed the need for many private ptrace requests,
so remove the corresponding definitions from the user-visible ptrace.h
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 60ffc30d5652810dd34ea2eec41504222f5d5791 |
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05-Mar-2012 |
Catalin Marinas <catalin.marinas@arm.com> |
arm64: Exception handling
The patch contains the exception entry code (kernel/entry.S), pt_regs
structure and related accessors, undefined instruction trapping and
stack tracing.
AArch64 Linux kernel (including kernel threads) runs in EL1 mode using
the SP1 stack. The vectors don't have a fixed address, only alignment
(2^11) requirements.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
|