ptrace.h revision f459f3db45c06394d3213ee5fa28f2f90326ce15 
1/*
2 * Based on arch/arm/include/asm/ptrace.h
3 *
4 * Copyright (C) 1996-2003 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_PTRACE_H
20#define __ASM_PTRACE_H
21
22#include <uapi/asm/ptrace.h>
23
24/* Current Exception Level values, as contained in CurrentEL */
25#define CurrentEL_EL1		(1 << 2)
26#define CurrentEL_EL2		(2 << 2)
27
28/* AArch32-specific ptrace requests */
29#define COMPAT_PTRACE_GETREGS		12
30#define COMPAT_PTRACE_SETREGS		13
31#define COMPAT_PTRACE_GET_THREAD_AREA	22
32#define COMPAT_PTRACE_SET_SYSCALL	23
33#define COMPAT_PTRACE_GETVFPREGS	27
34#define COMPAT_PTRACE_SETVFPREGS	28
35#define COMPAT_PTRACE_GETHBPREGS	29
36#define COMPAT_PTRACE_SETHBPREGS	30
37
38/* AArch32 CPSR bits */
39#define COMPAT_PSR_MODE_MASK	0x0000001f
40#define COMPAT_PSR_MODE_USR	0x00000010
41#define COMPAT_PSR_MODE_FIQ	0x00000011
42#define COMPAT_PSR_MODE_IRQ	0x00000012
43#define COMPAT_PSR_MODE_SVC	0x00000013
44#define COMPAT_PSR_MODE_ABT	0x00000017
45#define COMPAT_PSR_MODE_HYP	0x0000001a
46#define COMPAT_PSR_MODE_UND	0x0000001b
47#define COMPAT_PSR_MODE_SYS	0x0000001f
48#define COMPAT_PSR_T_BIT	0x00000020
49#define COMPAT_PSR_E_BIT	0x00000200
50#define COMPAT_PSR_F_BIT	0x00000040
51#define COMPAT_PSR_I_BIT	0x00000080
52#define COMPAT_PSR_A_BIT	0x00000100
53#define COMPAT_PSR_E_BIT	0x00000200
54#define COMPAT_PSR_J_BIT	0x01000000
55#define COMPAT_PSR_Q_BIT	0x08000000
56#define COMPAT_PSR_V_BIT	0x10000000
57#define COMPAT_PSR_C_BIT	0x20000000
58#define COMPAT_PSR_Z_BIT	0x40000000
59#define COMPAT_PSR_N_BIT	0x80000000
60#define COMPAT_PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
61/*
62 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
63 * process is located in memory.
64 */
65#define COMPAT_PT_TEXT_ADDR		0x10000
66#define COMPAT_PT_DATA_ADDR		0x10004
67#define COMPAT_PT_TEXT_END_ADDR		0x10008
68
69/*
70 * used to skip a system call when tracer changes its number to -1
71 * with ptrace(PTRACE_SET_SYSCALL)
72 */
73#define RET_SKIP_SYSCALL	-1
74#define IS_SKIP_SYSCALL(no)	((int)(no & 0xffffffff) == -1)
75
76#ifndef __ASSEMBLY__
77
78/* sizeof(struct user) for AArch32 */
79#define COMPAT_USER_SZ	296
80
81/* Architecturally defined mapping between AArch32 and AArch64 registers */
82#define compat_usr(x)	regs[(x)]
83#define compat_fp	regs[11]
84#define compat_sp	regs[13]
85#define compat_lr	regs[14]
86#define compat_sp_hyp	regs[15]
87#define compat_sp_irq	regs[16]
88#define compat_lr_irq	regs[17]
89#define compat_sp_svc	regs[18]
90#define compat_lr_svc	regs[19]
91#define compat_sp_abt	regs[20]
92#define compat_lr_abt	regs[21]
93#define compat_sp_und	regs[22]
94#define compat_lr_und	regs[23]
95#define compat_r8_fiq	regs[24]
96#define compat_r9_fiq	regs[25]
97#define compat_r10_fiq	regs[26]
98#define compat_r11_fiq	regs[27]
99#define compat_r12_fiq	regs[28]
100#define compat_sp_fiq	regs[29]
101#define compat_lr_fiq	regs[30]
102
103/*
104 * This struct defines the way the registers are stored on the stack during an
105 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
106 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
107 */
108struct pt_regs {
109	union {
110		struct user_pt_regs user_regs;
111		struct {
112			u64 regs[31];
113			u64 sp;
114			u64 pc;
115			u64 pstate;
116		};
117	};
118	u64 orig_x0;
119	u64 syscallno;
120};
121
122#define arch_has_single_step()	(1)
123
124#ifdef CONFIG_COMPAT
125#define compat_thumb_mode(regs) \
126	(((regs)->pstate & COMPAT_PSR_T_BIT))
127#else
128#define compat_thumb_mode(regs) (0)
129#endif
130
131#define user_mode(regs)	\
132	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
133
134#define compat_user_mode(regs)	\
135	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
136	 (PSR_MODE32_BIT | PSR_MODE_EL0t))
137
138#define processor_mode(regs) \
139	((regs)->pstate & PSR_MODE_MASK)
140
141#define interrupts_enabled(regs) \
142	(!((regs)->pstate & PSR_I_BIT))
143
144#define fast_interrupts_enabled(regs) \
145	(!((regs)->pstate & PSR_F_BIT))
146
147#define user_stack_pointer(regs) \
148	(!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
149
150static inline unsigned long regs_return_value(struct pt_regs *regs)
151{
152	return regs->regs[0];
153}
154
155/*
156 * Are the current registers suitable for user mode? (used to maintain
157 * security in signal handlers)
158 */
159static inline int valid_user_regs(struct user_pt_regs *regs)
160{
161	if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
162		regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
163
164		/* The T bit is reserved for AArch64 */
165		if (!(regs->pstate & PSR_MODE32_BIT))
166			regs->pstate &= ~COMPAT_PSR_T_BIT;
167
168		return 1;
169	}
170
171	/*
172	 * Force PSR to something logical...
173	 */
174	regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
175			COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
176
177	if (!(regs->pstate & PSR_MODE32_BIT)) {
178		regs->pstate &= ~COMPAT_PSR_T_BIT;
179		regs->pstate |= PSR_MODE_EL0t;
180	}
181
182	return 0;
183}
184
185#define instruction_pointer(regs)	((unsigned long)(regs)->pc)
186
187#ifdef CONFIG_SMP
188extern unsigned long profile_pc(struct pt_regs *regs);
189#else
190#define profile_pc(regs) instruction_pointer(regs)
191#endif
192
193/*
194 * True if instr is a 32-bit thumb instruction. This works if instr
195 * is the first or only half-word of a thumb instruction. It also works
196 * when instr holds all 32-bits of a wide thumb instruction if stored
197 * in the form (first_half<<16)|(second_half)
198 */
199#define is_wide_instruction(instr)	((unsigned)(instr) >= 0xe800)
200
201#endif /* __ASSEMBLY__ */
202#endif
203