1/* 2 * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory 3 * 4 * Copyright 2004-2008 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#ifndef __MEM_INIT_H__ 10#define __MEM_INIT_H__ 11 12#if defined(EBIU_SDGCTL) 13#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 14 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 15 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ 16 defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 17 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ 18 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 19 defined(CONFIG_MEM_MT48LC32M8A2_75) 20#if (CONFIG_SCLK_HZ > 119402985) 21#define SDRAM_tRP TRP_2 22#define SDRAM_tRP_num 2 23#define SDRAM_tRAS TRAS_7 24#define SDRAM_tRAS_num 7 25#define SDRAM_tRCD TRCD_2 26#define SDRAM_tWR TWR_2 27#endif 28#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) 29#define SDRAM_tRP TRP_2 30#define SDRAM_tRP_num 2 31#define SDRAM_tRAS TRAS_6 32#define SDRAM_tRAS_num 6 33#define SDRAM_tRCD TRCD_2 34#define SDRAM_tWR TWR_2 35#endif 36#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) 37#define SDRAM_tRP TRP_2 38#define SDRAM_tRP_num 2 39#define SDRAM_tRAS TRAS_5 40#define SDRAM_tRAS_num 5 41#define SDRAM_tRCD TRCD_2 42#define SDRAM_tWR TWR_2 43#endif 44#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) 45#define SDRAM_tRP TRP_2 46#define SDRAM_tRP_num 2 47#define SDRAM_tRAS TRAS_4 48#define SDRAM_tRAS_num 4 49#define SDRAM_tRCD TRCD_2 50#define SDRAM_tWR TWR_2 51#endif 52#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) 53#define SDRAM_tRP TRP_2 54#define SDRAM_tRP_num 2 55#define SDRAM_tRAS TRAS_3 56#define SDRAM_tRAS_num 3 57#define SDRAM_tRCD TRCD_2 58#define SDRAM_tWR TWR_2 59#endif 60#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) 61#define SDRAM_tRP TRP_1 62#define SDRAM_tRP_num 1 63#define SDRAM_tRAS TRAS_4 64#define SDRAM_tRAS_num 4 65#define SDRAM_tRCD TRCD_1 66#define SDRAM_tWR TWR_2 67#endif 68#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) 69#define SDRAM_tRP TRP_1 70#define SDRAM_tRP_num 1 71#define SDRAM_tRAS TRAS_3 72#define SDRAM_tRAS_num 3 73#define SDRAM_tRCD TRCD_1 74#define SDRAM_tWR TWR_2 75#endif 76#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) 77#define SDRAM_tRP TRP_1 78#define SDRAM_tRP_num 1 79#define SDRAM_tRAS TRAS_2 80#define SDRAM_tRAS_num 2 81#define SDRAM_tRCD TRCD_1 82#define SDRAM_tWR TWR_2 83#endif 84#if (CONFIG_SCLK_HZ <= 29850746) 85#define SDRAM_tRP TRP_1 86#define SDRAM_tRP_num 1 87#define SDRAM_tRAS TRAS_1 88#define SDRAM_tRAS_num 1 89#define SDRAM_tRCD TRCD_1 90#define SDRAM_tWR TWR_2 91#endif 92#endif 93 94/* 95 * The BF526-EZ-Board changed SDRAM chips between revisions, 96 * so we use below timings to accommodate both. 97 */ 98#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) 99#if (CONFIG_SCLK_HZ > 119402985) 100#define SDRAM_tRP TRP_2 101#define SDRAM_tRP_num 2 102#define SDRAM_tRAS TRAS_8 103#define SDRAM_tRAS_num 8 104#define SDRAM_tRCD TRCD_2 105#define SDRAM_tWR TWR_2 106#endif 107#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) 108#define SDRAM_tRP TRP_2 109#define SDRAM_tRP_num 2 110#define SDRAM_tRAS TRAS_7 111#define SDRAM_tRAS_num 7 112#define SDRAM_tRCD TRCD_2 113#define SDRAM_tWR TWR_2 114#endif 115#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) 116#define SDRAM_tRP TRP_2 117#define SDRAM_tRP_num 2 118#define SDRAM_tRAS TRAS_6 119#define SDRAM_tRAS_num 6 120#define SDRAM_tRCD TRCD_2 121#define SDRAM_tWR TWR_2 122#endif 123#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) 124#define SDRAM_tRP TRP_2 125#define SDRAM_tRP_num 2 126#define SDRAM_tRAS TRAS_5 127#define SDRAM_tRAS_num 5 128#define SDRAM_tRCD TRCD_2 129#define SDRAM_tWR TWR_2 130#endif 131#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) 132#define SDRAM_tRP TRP_2 133#define SDRAM_tRP_num 2 134#define SDRAM_tRAS TRAS_4 135#define SDRAM_tRAS_num 4 136#define SDRAM_tRCD TRCD_2 137#define SDRAM_tWR TWR_2 138#endif 139#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) 140#define SDRAM_tRP TRP_2 141#define SDRAM_tRP_num 2 142#define SDRAM_tRAS TRAS_4 143#define SDRAM_tRAS_num 4 144#define SDRAM_tRCD TRCD_1 145#define SDRAM_tWR TWR_2 146#endif 147#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) 148#define SDRAM_tRP TRP_2 149#define SDRAM_tRP_num 2 150#define SDRAM_tRAS TRAS_3 151#define SDRAM_tRAS_num 3 152#define SDRAM_tRCD TRCD_1 153#define SDRAM_tWR TWR_2 154#endif 155#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) 156#define SDRAM_tRP TRP_1 157#define SDRAM_tRP_num 1 158#define SDRAM_tRAS TRAS_3 159#define SDRAM_tRAS_num 3 160#define SDRAM_tRCD TRCD_1 161#define SDRAM_tWR TWR_2 162#endif 163#if (CONFIG_SCLK_HZ <= 29850746) 164#define SDRAM_tRP TRP_1 165#define SDRAM_tRP_num 1 166#define SDRAM_tRAS TRAS_2 167#define SDRAM_tRAS_num 2 168#define SDRAM_tRCD TRCD_1 169#define SDRAM_tWR TWR_2 170#endif 171#endif 172 173#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ 174 defined(CONFIG_MEM_MT48LC8M32B2B5_7) 175 /*SDRAM INFORMATION: */ 176#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 177#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ 178#define SDRAM_CL CL_3 179#endif 180 181#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 182 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 183 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 184 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 185 defined(CONFIG_MEM_MT48LC32M8A2_75) 186 /*SDRAM INFORMATION: */ 187#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 188#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 189#define SDRAM_CL CL_3 190#endif 191 192#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) 193 /*SDRAM INFORMATION: */ 194#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 195#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 196#define SDRAM_CL CL_2 197#endif 198 199 200#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC 201/* Equation from section 17 (p17-46) of BF533 HRM */ 202#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) 203 204/* Enable SCLK Out */ 205#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) 206#else 207#define mem_SDRRC CONFIG_MEM_SDRRC 208#define mem_SDGCTL CONFIG_MEM_SDGCTL 209#endif 210#endif 211 212 213#if defined(EBIU_DDRCTL0) 214#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) 215#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) 216#define DDR_CLK_HZ(x) (1000*1000*1000/x) 217 218#if defined(CONFIG_MEM_MT46V32M16_6T) 219#define DDR_SIZE DEVSZ_512 220#define DDR_WIDTH DEVWD_16 221#define DDR_MAX_tCK 13 222 223#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) 224#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) 225#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) 226#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) 227#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) 228 229#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) 230#define DDR_tWTR DDR_TWTR(1) 231#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) 232#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) 233#endif 234 235#if defined(CONFIG_MEM_MT46V32M16_5B) 236#define DDR_SIZE DEVSZ_512 237#define DDR_WIDTH DEVWD_16 238#define DDR_MAX_tCK 13 239 240#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) 241#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) 242#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) 243#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) 244#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) 245 246#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) 247#define DDR_tWTR DDR_TWTR(2) 248#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) 249#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) 250#endif 251 252#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) 253# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." 254#elif(CONFIG_SCLK_HZ <= 133333333) 255# define DDR_CL CL_2 256#else 257# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)." 258#endif 259 260#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC 261#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) 262#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ 263 | DDR_tMRD | DDR_tWR | DDR_tRCD) 264#define mem_DDRCTL2 DDR_CL 265#else 266#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0 267#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1 268#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2 269#endif 270#endif 271 272#if defined CONFIG_CLKIN_HALF 273#define CLKIN_HALF 1 274#else 275#define CLKIN_HALF 0 276#endif 277 278#if defined CONFIG_PLL_BYPASS 279#define PLL_BYPASS 1 280#else 281#define PLL_BYPASS 0 282#endif 283 284#ifdef CONFIG_BF60x 285 286/* DMC status bits */ 287#define IDLE 0x1 288#define MEMINITDONE 0x4 289#define SRACK 0x8 290#define PDACK 0x10 291#define DPDACK 0x20 292#define DLLCALDONE 0x2000 293#define PENDREF 0xF0000 294#define PHYRDPHASE 0xF00000 295#define PHYRDPHASE_OFFSET 20 296 297/* DMC control bits */ 298#define LPDDR 0x2 299#define INIT 0x4 300#define SRREQ 0x8 301#define PDREQ 0x10 302#define DPDREQ 0x20 303#define PREC 0x40 304#define ADDRMODE 0x100 305#define RDTOWR 0xE00 306#define PPREF 0x1000 307#define DLLCAL 0x2000 308 309/* DMC DLL control bits */ 310#define DLLCALRDCNT 0xFF 311#define DATACYC 0xF00 312#define DATACYC_OFFSET 8 313 314/* CGU Divisor bits */ 315#define CSEL_OFFSET 0 316#define S0SEL_OFFSET 5 317#define SYSSEL_OFFSET 8 318#define S1SEL_OFFSET 13 319#define DSEL_OFFSET 16 320#define OSEL_OFFSET 22 321#define ALGN 0x20000000 322#define UPDT 0x40000000 323#define LOCK 0x80000000 324 325/* CGU Status bits */ 326#define PLLEN 0x1 327#define PLLBP 0x2 328#define PLOCK 0x4 329#define CLKSALGN 0x8 330 331/* CGU Control bits */ 332#define MSEL_MASK 0x7F00 333#define DF_MASK 0x1 334 335struct ddr_config { 336 u32 ddr_clk; 337 u32 dmc_ddrctl; 338 u32 dmc_effctl; 339 u32 dmc_ddrcfg; 340 u32 dmc_ddrtr0; 341 u32 dmc_ddrtr1; 342 u32 dmc_ddrtr2; 343 u32 dmc_ddrmr; 344 u32 dmc_ddrmr1; 345}; 346 347#if defined(CONFIG_MEM_MT47H64M16) 348static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { 349 [0] = { 350 .ddr_clk = 125, 351 .dmc_ddrctl = 0x00000904, 352 .dmc_effctl = 0x004400C0, 353 .dmc_ddrcfg = 0x00000422, 354 .dmc_ddrtr0 = 0x20705212, 355 .dmc_ddrtr1 = 0x201003CF, 356 .dmc_ddrtr2 = 0x00320107, 357 .dmc_ddrmr = 0x00000422, 358 .dmc_ddrmr1 = 0x4, 359 }, 360 [1] = { 361 .ddr_clk = 133, 362 .dmc_ddrctl = 0x00000904, 363 .dmc_effctl = 0x004400C0, 364 .dmc_ddrcfg = 0x00000422, 365 .dmc_ddrtr0 = 0x20806313, 366 .dmc_ddrtr1 = 0x2013040D, 367 .dmc_ddrtr2 = 0x00320108, 368 .dmc_ddrmr = 0x00000632, 369 .dmc_ddrmr1 = 0x4, 370 }, 371 [2] = { 372 .ddr_clk = 150, 373 .dmc_ddrctl = 0x00000904, 374 .dmc_effctl = 0x004400C0, 375 .dmc_ddrcfg = 0x00000422, 376 .dmc_ddrtr0 = 0x20A07323, 377 .dmc_ddrtr1 = 0x20160492, 378 .dmc_ddrtr2 = 0x00320209, 379 .dmc_ddrmr = 0x00000632, 380 .dmc_ddrmr1 = 0x4, 381 }, 382 [3] = { 383 .ddr_clk = 166, 384 .dmc_ddrctl = 0x00000904, 385 .dmc_effctl = 0x004400C0, 386 .dmc_ddrcfg = 0x00000422, 387 .dmc_ddrtr0 = 0x20A07323, 388 .dmc_ddrtr1 = 0x2016050E, 389 .dmc_ddrtr2 = 0x00320209, 390 .dmc_ddrmr = 0x00000632, 391 .dmc_ddrmr1 = 0x4, 392 }, 393 [4] = { 394 .ddr_clk = 200, 395 .dmc_ddrctl = 0x00000904, 396 .dmc_effctl = 0x004400C0, 397 .dmc_ddrcfg = 0x00000422, 398 .dmc_ddrtr0 = 0x20a07323, 399 .dmc_ddrtr1 = 0x2016050f, 400 .dmc_ddrtr2 = 0x00320509, 401 .dmc_ddrmr = 0x00000632, 402 .dmc_ddrmr1 = 0x4, 403 }, 404 [5] = { 405 .ddr_clk = 225, 406 .dmc_ddrctl = 0x00000904, 407 .dmc_effctl = 0x004400C0, 408 .dmc_ddrcfg = 0x00000422, 409 .dmc_ddrtr0 = 0x20E0A424, 410 .dmc_ddrtr1 = 0x302006DB, 411 .dmc_ddrtr2 = 0x0032020D, 412 .dmc_ddrmr = 0x00000842, 413 .dmc_ddrmr1 = 0x4, 414 }, 415 [6] = { 416 .ddr_clk = 250, 417 .dmc_ddrctl = 0x00000904, 418 .dmc_effctl = 0x004400C0, 419 .dmc_ddrcfg = 0x00000422, 420 .dmc_ddrtr0 = 0x20E0A424, 421 .dmc_ddrtr1 = 0x3020079E, 422 .dmc_ddrtr2 = 0x0032050D, 423 .dmc_ddrmr = 0x00000842, 424 .dmc_ddrmr1 = 0x4, 425 }, 426}; 427#endif 428 429static inline void dmc_enter_self_refresh(void) 430{ 431 if (bfin_read_DMC0_STAT() & MEMINITDONE) { 432 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); 433 while (!(bfin_read_DMC0_STAT() & SRACK)) 434 continue; 435 } 436} 437 438static inline void dmc_exit_self_refresh(void) 439{ 440 if (bfin_read_DMC0_STAT() & MEMINITDONE) { 441 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); 442 while (bfin_read_DMC0_STAT() & SRACK) 443 continue; 444 } 445} 446 447static inline void init_cgu(u32 cgu_div, u32 cgu_ctl) 448{ 449 dmc_enter_self_refresh(); 450 451 /* Don't set the same value of MSEL and DF to CGU_CTL */ 452 if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) 453 != cgu_ctl) { 454 bfin_write32(CGU0_DIV, cgu_div); 455 bfin_write32(CGU0_CTL, cgu_ctl); 456 while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || 457 !(bfin_read32(CGU0_STAT) & PLOCK)) 458 continue; 459 } 460 461 bfin_write32(CGU0_DIV, cgu_div | UPDT); 462 while (bfin_read32(CGU0_STAT) & CLKSALGN) 463 continue; 464 465 dmc_exit_self_refresh(); 466} 467 468static inline void init_dmc(u32 dmc_clk) 469{ 470 int i, dlldatacycle, dll_ctl; 471 472 for (i = 0; i < 7; i++) { 473 if (ddr_config_table[i].ddr_clk == dmc_clk) { 474 bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); 475 bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); 476 bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); 477 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); 478 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); 479 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); 480 bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl); 481 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); 482 break; 483 } 484 } 485 486 while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) 487 continue; 488 489 dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; 490 dll_ctl = bfin_read_DMC0_DLLCTL(); 491 dll_ctl &= ~DATACYC; 492 bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); 493 494 while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) 495 continue; 496} 497#endif 498 499#endif /*__MEM_INIT_H__*/ 500 501