1 2/* 3 * 68360 Communication Processor Module. 4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after: 5 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx) 6 * 7 * This file contains structures and information for the communication 8 * processor channels. Some CPM control and status is available 9 * through the 68360 internal memory map. See include/asm/360_immap.h for details. 10 * This file is not a complete map of all of the 360 QUICC's capabilities 11 * 12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 13 * bytes of the DP RAM and relocates the I2C parameter area to the 14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 15 * or other use. 16 */ 17#ifndef __CPM_360__ 18#define __CPM_360__ 19 20 21/* CPM Command register masks: */ 22#define CPM_CR_RST ((ushort)0x8000) 23#define CPM_CR_OPCODE ((ushort)0x0f00) 24#define CPM_CR_CHAN ((ushort)0x00f0) 25#define CPM_CR_FLG ((ushort)0x0001) 26 27/* CPM Command set (opcodes): */ 28#define CPM_CR_INIT_TRX ((ushort)0x0000) 29#define CPM_CR_INIT_RX ((ushort)0x0001) 30#define CPM_CR_INIT_TX ((ushort)0x0002) 31#define CPM_CR_HUNT_MODE ((ushort)0x0003) 32#define CPM_CR_STOP_TX ((ushort)0x0004) 33#define CPM_CR_GRSTOP_TX ((ushort)0x0005) 34#define CPM_CR_RESTART_TX ((ushort)0x0006) 35#define CPM_CR_CLOSE_RXBD ((ushort)0x0007) 36#define CPM_CR_SET_GADDR ((ushort)0x0008) 37#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009) 38#define CPM_CR_GCI_ABORT ((ushort)0x000a) 39#define CPM_CR_RESET_BCS ((ushort)0x000a) 40 41/* CPM Channel numbers. */ 42#define CPM_CR_CH_SCC1 ((ushort)0x0000) 43#define CPM_CR_CH_SCC2 ((ushort)0x0004) 44#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */ 45#define CPM_CR_CH_TMR ((ushort)0x0005) 46#define CPM_CR_CH_SCC3 ((ushort)0x0008) 47#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */ 48#define CPM_CR_CH_IDMA1 ((ushort)0x0009) 49#define CPM_CR_CH_SCC4 ((ushort)0x000c) 50#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */ 51#define CPM_CR_CH_IDMA2 ((ushort)0x000d) 52 53 54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) 55 56#if 1 /* mleslie: I dinna think we have any such restrictions on 57 * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */ 58 59/* The dual ported RAM is multi-functional. Some areas can be (and are 60 * being) used for microcode. There is an area that can only be used 61 * as data ram for buffer descriptors, which is all we use right now. 62 * Currently the first 512 and last 256 bytes are used for microcode. 63 */ 64/* mleslie: The uCquicc board is using no extra microcode in DPRAM */ 65#define CPM_DATAONLY_BASE ((uint)0x0000) 66#define CPM_DATAONLY_SIZE ((uint)0x0800) 67#define CPM_DP_NOSPACE ((uint)0x7fffffff) 68 69#endif 70 71 72/* Export the base address of the communication processor registers 73 * and dual port ram. */ 74/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */ 75extern QUICC *pquicc; 76uint m360_cpm_dpalloc(uint size); 77/* void *m360_cpm_hostalloc(uint size); */ 78void m360_cpm_setbrg(uint brg, uint rate); 79 80#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */ 81/* Buffer descriptors used by many of the CPM protocols. */ 82typedef struct cpm_buf_desc { 83 ushort cbd_sc; /* Status and Control */ 84 ushort cbd_datlen; /* Data length in buffer */ 85 uint cbd_bufaddr; /* Buffer address in host memory */ 86} cbd_t; 87#endif 88 89 90/* rx bd status/control bits */ 91#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ 93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ 95 96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ 97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ 98 99#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ 101 102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ 103#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */ 104 105#define BD_SC_BR ((ushort)0x0020) /* Break received */ 106#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */ 107 108#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 109#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */ 110 111#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 112#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */ 113 114#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 115#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ 116 117/* tx bd status/control bits (as differ from rx bd) */ 118#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 119#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 120#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 121#define BD_SC_UN ((ushort)0x0002) /* Underrun */ 122 123 124 125 126/* Parameter RAM offsets. */ 127 128 129 130/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM. 131 * In 2.0, we use a more structured C struct map of DPRAM, and so 132 * instead, we need only a parameter ram `slot' */ 133 134#define PRSLOT_SCC1 0 135#define PRSLOT_SCC2 1 136#define PRSLOT_SCC3 2 137#define PRSLOT_SMC1 2 138#define PRSLOT_SCC4 3 139#define PRSLOT_SMC2 3 140 141 142/* #define PROFF_SCC1 ((uint)0x0000) */ 143/* #define PROFF_SCC2 ((uint)0x0100) */ 144/* #define PROFF_SCC3 ((uint)0x0200) */ 145/* #define PROFF_SMC1 ((uint)0x0280) */ 146/* #define PROFF_SCC4 ((uint)0x0300) */ 147/* #define PROFF_SMC2 ((uint)0x0380) */ 148 149 150/* Define enough so I can at least use the serial port as a UART. 151 * The MBX uses SMC1 as the host serial port. 152 */ 153typedef struct smc_uart { 154 ushort smc_rbase; /* Rx Buffer descriptor base address */ 155 ushort smc_tbase; /* Tx Buffer descriptor base address */ 156 u_char smc_rfcr; /* Rx function code */ 157 u_char smc_tfcr; /* Tx function code */ 158 ushort smc_mrblr; /* Max receive buffer length */ 159 uint smc_rstate; /* Internal */ 160 uint smc_idp; /* Internal */ 161 ushort smc_rbptr; /* Internal */ 162 ushort smc_ibc; /* Internal */ 163 uint smc_rxtmp; /* Internal */ 164 uint smc_tstate; /* Internal */ 165 uint smc_tdp; /* Internal */ 166 ushort smc_tbptr; /* Internal */ 167 ushort smc_tbc; /* Internal */ 168 uint smc_txtmp; /* Internal */ 169 ushort smc_maxidl; /* Maximum idle characters */ 170 ushort smc_tmpidl; /* Temporary idle counter */ 171 ushort smc_brklen; /* Last received break length */ 172 ushort smc_brkec; /* rcv'd break condition counter */ 173 ushort smc_brkcr; /* xmt break count register */ 174 ushort smc_rmask; /* Temporary bit mask */ 175} smc_uart_t; 176 177/* Function code bits. 178*/ 179#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ 180 181/* SMC uart mode register. 182*/ 183#define SMCMR_REN ((ushort)0x0001) 184#define SMCMR_TEN ((ushort)0x0002) 185#define SMCMR_DM ((ushort)0x000c) 186#define SMCMR_SM_GCI ((ushort)0x0000) 187#define SMCMR_SM_UART ((ushort)0x0020) 188#define SMCMR_SM_TRANS ((ushort)0x0030) 189#define SMCMR_SM_MASK ((ushort)0x0030) 190#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 191#define SMCMR_REVD SMCMR_PM_EVEN 192#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 193#define SMCMR_BS SMCMR_PEN 194#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 195#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 196#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 197 198/* SMC2 as Centronics parallel printer. It is half duplex, in that 199 * it can only receive or transmit. The parameter ram values for 200 * each direction are either unique or properly overlap, so we can 201 * include them in one structure. 202 */ 203typedef struct smc_centronics { 204 ushort scent_rbase; 205 ushort scent_tbase; 206 u_char scent_cfcr; 207 u_char scent_smask; 208 ushort scent_mrblr; 209 uint scent_rstate; 210 uint scent_r_ptr; 211 ushort scent_rbptr; 212 ushort scent_r_cnt; 213 uint scent_rtemp; 214 uint scent_tstate; 215 uint scent_t_ptr; 216 ushort scent_tbptr; 217 ushort scent_t_cnt; 218 uint scent_ttemp; 219 ushort scent_max_sl; 220 ushort scent_sl_cnt; 221 ushort scent_character1; 222 ushort scent_character2; 223 ushort scent_character3; 224 ushort scent_character4; 225 ushort scent_character5; 226 ushort scent_character6; 227 ushort scent_character7; 228 ushort scent_character8; 229 ushort scent_rccm; 230 ushort scent_rccr; 231} smc_cent_t; 232 233/* Centronics Status Mask Register. 234*/ 235#define SMC_CENT_F ((u_char)0x08) 236#define SMC_CENT_PE ((u_char)0x04) 237#define SMC_CENT_S ((u_char)0x02) 238 239/* SMC Event and Mask register. 240*/ 241#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 242#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 243#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ 244#define SMCM_BSY ((unsigned char)0x04) 245#define SMCM_TX ((unsigned char)0x02) 246#define SMCM_RX ((unsigned char)0x01) 247 248/* Baud rate generators. 249*/ 250#define CPM_BRG_RST ((uint)0x00020000) 251#define CPM_BRG_EN ((uint)0x00010000) 252#define CPM_BRG_EXTC_INT ((uint)0x00000000) 253#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) 254#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) 255#define CPM_BRG_ATB ((uint)0x00002000) 256#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 257#define CPM_BRG_DIV16 ((uint)0x00000001) 258 259/* SCCs. 260*/ 261#define SCC_GSMRH_IRP ((uint)0x00040000) 262#define SCC_GSMRH_GDE ((uint)0x00010000) 263#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 264#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 265#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 266#define SCC_GSMRH_REVD ((uint)0x00002000) 267#define SCC_GSMRH_TRX ((uint)0x00001000) 268#define SCC_GSMRH_TTX ((uint)0x00000800) 269#define SCC_GSMRH_CDP ((uint)0x00000400) 270#define SCC_GSMRH_CTSP ((uint)0x00000200) 271#define SCC_GSMRH_CDS ((uint)0x00000100) 272#define SCC_GSMRH_CTSS ((uint)0x00000080) 273#define SCC_GSMRH_TFL ((uint)0x00000040) 274#define SCC_GSMRH_RFW ((uint)0x00000020) 275#define SCC_GSMRH_TXSY ((uint)0x00000010) 276#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 277#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 278#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 279#define SCC_GSMRH_RTSM ((uint)0x00000002) 280#define SCC_GSMRH_RSYN ((uint)0x00000001) 281 282#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 283#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 284#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 285#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 286#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 287#define SCC_GSMRL_TCI ((uint)0x10000000) 288#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 289#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 290#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 291#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 292#define SCC_GSMRL_RINV ((uint)0x02000000) 293#define SCC_GSMRL_TINV ((uint)0x01000000) 294#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 295#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 296#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 297#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 298#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 299#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 300#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 301#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 302#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 303#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 304#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 305#define SCC_GSMRL_TEND ((uint)0x00040000) 306#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 307#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 308#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 309#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 310#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 311#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 312#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 313#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 314#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 315#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 316#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 317#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 318#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 319#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 320#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 321#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 322#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 323#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 324#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 325#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 326#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 327#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 328#define SCC_GSMRL_ENR ((uint)0x00000020) 329#define SCC_GSMRL_ENT ((uint)0x00000010) 330#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 331#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 332#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 333#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 334#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 335#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 336#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 337#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 338#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 339#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 340 341#define SCC_TODR_TOD ((ushort)0x8000) 342 343/* SCC Event and Mask register. 344*/ 345#define SCCM_TXE ((unsigned char)0x10) 346#define SCCM_BSY ((unsigned char)0x04) 347#define SCCM_TX ((unsigned char)0x02) 348#define SCCM_RX ((unsigned char)0x01) 349 350typedef struct scc_param { 351 ushort scc_rbase; /* Rx Buffer descriptor base address */ 352 ushort scc_tbase; /* Tx Buffer descriptor base address */ 353 u_char scc_rfcr; /* Rx function code */ 354 u_char scc_tfcr; /* Tx function code */ 355 ushort scc_mrblr; /* Max receive buffer length */ 356 uint scc_rstate; /* Internal */ 357 uint scc_idp; /* Internal */ 358 ushort scc_rbptr; /* Internal */ 359 ushort scc_ibc; /* Internal */ 360 uint scc_rxtmp; /* Internal */ 361 uint scc_tstate; /* Internal */ 362 uint scc_tdp; /* Internal */ 363 ushort scc_tbptr; /* Internal */ 364 ushort scc_tbc; /* Internal */ 365 uint scc_txtmp; /* Internal */ 366 uint scc_rcrc; /* Internal */ 367 uint scc_tcrc; /* Internal */ 368} sccp_t; 369 370 371/* Function code bits. 372 */ 373#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ 374#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */ 375 376/* CPM Ethernet through SCC1. 377 */ 378typedef struct scc_enet { 379 sccp_t sen_genscc; 380 uint sen_cpres; /* Preset CRC */ 381 uint sen_cmask; /* Constant mask for CRC */ 382 uint sen_crcec; /* CRC Error counter */ 383 uint sen_alec; /* alignment error counter */ 384 uint sen_disfc; /* discard frame counter */ 385 ushort sen_pads; /* Tx short frame pad character */ 386 ushort sen_retlim; /* Retry limit threshold */ 387 ushort sen_retcnt; /* Retry limit counter */ 388 ushort sen_maxflr; /* maximum frame length register */ 389 ushort sen_minflr; /* minimum frame length register */ 390 ushort sen_maxd1; /* maximum DMA1 length */ 391 ushort sen_maxd2; /* maximum DMA2 length */ 392 ushort sen_maxd; /* Rx max DMA */ 393 ushort sen_dmacnt; /* Rx DMA counter */ 394 ushort sen_maxb; /* Max BD byte count */ 395 ushort sen_gaddr1; /* Group address filter */ 396 ushort sen_gaddr2; 397 ushort sen_gaddr3; 398 ushort sen_gaddr4; 399 uint sen_tbuf0data0; /* Save area 0 - current frame */ 400 uint sen_tbuf0data1; /* Save area 1 - current frame */ 401 uint sen_tbuf0rba; /* Internal */ 402 uint sen_tbuf0crc; /* Internal */ 403 ushort sen_tbuf0bcnt; /* Internal */ 404 ushort sen_paddrh; /* physical address (MSB) */ 405 ushort sen_paddrm; 406 ushort sen_paddrl; /* physical address (LSB) */ 407 ushort sen_pper; /* persistence */ 408 ushort sen_rfbdptr; /* Rx first BD pointer */ 409 ushort sen_tfbdptr; /* Tx first BD pointer */ 410 ushort sen_tlbdptr; /* Tx last BD pointer */ 411 uint sen_tbuf1data0; /* Save area 0 - current frame */ 412 uint sen_tbuf1data1; /* Save area 1 - current frame */ 413 uint sen_tbuf1rba; /* Internal */ 414 uint sen_tbuf1crc; /* Internal */ 415 ushort sen_tbuf1bcnt; /* Internal */ 416 ushort sen_txlen; /* Tx Frame length counter */ 417 ushort sen_iaddr1; /* Individual address filter */ 418 ushort sen_iaddr2; 419 ushort sen_iaddr3; 420 ushort sen_iaddr4; 421 ushort sen_boffcnt; /* Backoff counter */ 422 423 /* NOTE: Some versions of the manual have the following items 424 * incorrectly documented. Below is the proper order. 425 */ 426 ushort sen_taddrh; /* temp address (MSB) */ 427 ushort sen_taddrm; 428 ushort sen_taddrl; /* temp address (LSB) */ 429} scc_enet_t; 430 431 432 433#if defined (CONFIG_UCQUICC) 434/* uCquicc has the following signals connected to Ethernet: 435 * 68360 - lxt905 436 * PA0/RXD1 - rxd 437 * PA1/TXD1 - txd 438 * PA8/CLK1 - tclk 439 * PA9/CLK2 - rclk 440 * PC0/!RTS1 - t_en 441 * PC1/!CTS1 - col 442 * PC5/!CD1 - cd 443 */ 444#define PA_ENET_RXD PA_RXD1 445#define PA_ENET_TXD PA_TXD1 446#define PA_ENET_TCLK PA_CLK1 447#define PA_ENET_RCLK PA_CLK2 448#define PC_ENET_TENA PC_RTS1 449#define PC_ENET_CLSN PC_CTS1 450#define PC_ENET_RENA PC_CD1 451 452/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to 453 * SCC1. 454 */ 455#define SICR_ENET_MASK ((uint)0x000000ff) 456#define SICR_ENET_CLKRT ((uint)0x0000002c) 457 458#endif /* config_ucquicc */ 459 460 461#ifdef MBX 462/* Bits in parallel I/O port registers that have to be set/cleared 463 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique 464 * to the MBX860 board. Any two of the four available clocks could be 465 * used, and the MPC860 cookbook manual has an example using different 466 * clock pins. 467 */ 468#define PA_ENET_RXD ((ushort)0x0001) 469#define PA_ENET_TXD ((ushort)0x0002) 470#define PA_ENET_TCLK ((ushort)0x0200) 471#define PA_ENET_RCLK ((ushort)0x0800) 472#define PC_ENET_TENA ((ushort)0x0001) 473#define PC_ENET_CLSN ((ushort)0x0010) 474#define PC_ENET_RENA ((ushort)0x0020) 475 476/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 477 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 478 */ 479#define SICR_ENET_MASK ((uint)0x000000ff) 480#define SICR_ENET_CLKRT ((uint)0x0000003d) 481#endif 482 483#ifdef CONFIG_BSEIP 484/* This ENET stuff is for the MPC823 with ethernet on SCC2. 485 * This is unique to the BSE ip-Engine board. 486 */ 487#define PA_ENET_RXD ((ushort)0x0004) 488#define PA_ENET_TXD ((ushort)0x0008) 489#define PA_ENET_TCLK ((ushort)0x0100) 490#define PA_ENET_RCLK ((ushort)0x0200) 491#define PB_ENET_TENA ((uint)0x00002000) 492#define PC_ENET_CLSN ((ushort)0x0040) 493#define PC_ENET_RENA ((ushort)0x0080) 494 495/* BSE uses port B and C bits for PHY control also. 496*/ 497#define PB_BSE_POWERUP ((uint)0x00000004) 498#define PB_BSE_FDXDIS ((uint)0x00008000) 499#define PC_BSE_LOOPBACK ((ushort)0x0800) 500 501#define SICR_ENET_MASK ((uint)0x0000ff00) 502#define SICR_ENET_CLKRT ((uint)0x00002c00) 503#endif 504 505/* SCC Event register as used by Ethernet. 506*/ 507#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 508#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 509#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 510#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 511#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 512#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 513 514/* SCC Mode Register (PMSR) as used by Ethernet. 515*/ 516#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */ 517#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */ 518#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */ 519#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */ 520#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 521#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */ 522#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 523#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */ 524#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */ 525#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */ 526#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */ 527#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */ 528#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */ 529 530/* Buffer descriptor control/status used by Ethernet receive. 531*/ 532#define BD_ENET_RX_EMPTY ((ushort)0x8000) 533#define BD_ENET_RX_WRAP ((ushort)0x2000) 534#define BD_ENET_RX_INTR ((ushort)0x1000) 535#define BD_ENET_RX_LAST ((ushort)0x0800) 536#define BD_ENET_RX_FIRST ((ushort)0x0400) 537#define BD_ENET_RX_MISS ((ushort)0x0100) 538#define BD_ENET_RX_LG ((ushort)0x0020) 539#define BD_ENET_RX_NO ((ushort)0x0010) 540#define BD_ENET_RX_SH ((ushort)0x0008) 541#define BD_ENET_RX_CR ((ushort)0x0004) 542#define BD_ENET_RX_OV ((ushort)0x0002) 543#define BD_ENET_RX_CL ((ushort)0x0001) 544#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 545 546/* Buffer descriptor control/status used by Ethernet transmit. 547*/ 548#define BD_ENET_TX_READY ((ushort)0x8000) 549#define BD_ENET_TX_PAD ((ushort)0x4000) 550#define BD_ENET_TX_WRAP ((ushort)0x2000) 551#define BD_ENET_TX_INTR ((ushort)0x1000) 552#define BD_ENET_TX_LAST ((ushort)0x0800) 553#define BD_ENET_TX_TC ((ushort)0x0400) 554#define BD_ENET_TX_DEF ((ushort)0x0200) 555#define BD_ENET_TX_HB ((ushort)0x0100) 556#define BD_ENET_TX_LC ((ushort)0x0080) 557#define BD_ENET_TX_RL ((ushort)0x0040) 558#define BD_ENET_TX_RCMASK ((ushort)0x003c) 559#define BD_ENET_TX_UN ((ushort)0x0002) 560#define BD_ENET_TX_CSL ((ushort)0x0001) 561#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 562 563/* SCC as UART 564*/ 565typedef struct scc_uart { 566 sccp_t scc_genscc; 567 uint scc_res1; /* Reserved */ 568 uint scc_res2; /* Reserved */ 569 ushort scc_maxidl; /* Maximum idle chars */ 570 ushort scc_idlc; /* temp idle counter */ 571 ushort scc_brkcr; /* Break count register */ 572 ushort scc_parec; /* receive parity error counter */ 573 ushort scc_frmec; /* receive framing error counter */ 574 ushort scc_nosec; /* receive noise counter */ 575 ushort scc_brkec; /* receive break condition counter */ 576 ushort scc_brkln; /* last received break length */ 577 ushort scc_uaddr1; /* UART address character 1 */ 578 ushort scc_uaddr2; /* UART address character 2 */ 579 ushort scc_rtemp; /* Temp storage */ 580 ushort scc_toseq; /* Transmit out of sequence char */ 581 ushort scc_char1; /* control character 1 */ 582 ushort scc_char2; /* control character 2 */ 583 ushort scc_char3; /* control character 3 */ 584 ushort scc_char4; /* control character 4 */ 585 ushort scc_char5; /* control character 5 */ 586 ushort scc_char6; /* control character 6 */ 587 ushort scc_char7; /* control character 7 */ 588 ushort scc_char8; /* control character 8 */ 589 ushort scc_rccm; /* receive control character mask */ 590 ushort scc_rccr; /* receive control character register */ 591 ushort scc_rlbc; /* receive last break character */ 592} scc_uart_t; 593 594/* SCC Event and Mask registers when it is used as a UART. 595*/ 596#define UART_SCCM_GLR ((ushort)0x1000) 597#define UART_SCCM_GLT ((ushort)0x0800) 598#define UART_SCCM_AB ((ushort)0x0200) 599#define UART_SCCM_IDL ((ushort)0x0100) 600#define UART_SCCM_GRA ((ushort)0x0080) 601#define UART_SCCM_BRKE ((ushort)0x0040) 602#define UART_SCCM_BRKS ((ushort)0x0020) 603#define UART_SCCM_CCR ((ushort)0x0008) 604#define UART_SCCM_BSY ((ushort)0x0004) 605#define UART_SCCM_TX ((ushort)0x0002) 606#define UART_SCCM_RX ((ushort)0x0001) 607 608/* The SCC PMSR when used as a UART. 609*/ 610#define SCU_PMSR_FLC ((ushort)0x8000) 611#define SCU_PMSR_SL ((ushort)0x4000) 612#define SCU_PMSR_CL ((ushort)0x3000) 613#define SCU_PMSR_UM ((ushort)0x0c00) 614#define SCU_PMSR_FRZ ((ushort)0x0200) 615#define SCU_PMSR_RZS ((ushort)0x0100) 616#define SCU_PMSR_SYN ((ushort)0x0080) 617#define SCU_PMSR_DRT ((ushort)0x0040) 618#define SCU_PMSR_PEN ((ushort)0x0010) 619#define SCU_PMSR_RPM ((ushort)0x000c) 620#define SCU_PMSR_REVP ((ushort)0x0008) 621#define SCU_PMSR_TPM ((ushort)0x0003) 622#define SCU_PMSR_TEVP ((ushort)0x0003) 623 624/* CPM Transparent mode SCC. 625 */ 626typedef struct scc_trans { 627 sccp_t st_genscc; 628 uint st_cpres; /* Preset CRC */ 629 uint st_cmask; /* Constant mask for CRC */ 630} scc_trans_t; 631 632#define BD_SCC_TX_LAST ((ushort)0x0800) 633 634 635 636/* CPM interrupts. There are nearly 32 interrupts generated by CPM 637 * channels or devices. All of these are presented to the PPC core 638 * as a single interrupt. The CPM interrupt handler dispatches its 639 * own handlers, in a similar fashion to the PPC core handler. We 640 * use the table as defined in the manuals (i.e. no special high 641 * priority and SCC1 == SCCa, etc...). 642 */ 643/* #define CPMVEC_NR 32 */ 644/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */ 645/* #define CPMVEC_SCC1 ((ushort)0x1e) */ 646/* #define CPMVEC_SCC2 ((ushort)0x1d) */ 647/* #define CPMVEC_SCC3 ((ushort)0x1c) */ 648/* #define CPMVEC_SCC4 ((ushort)0x1b) */ 649/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */ 650/* #define CPMVEC_TIMER1 ((ushort)0x19) */ 651/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */ 652/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */ 653/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ 654/* #define CPMVEC_IDMA1 ((ushort)0x15) */ 655/* #define CPMVEC_IDMA2 ((ushort)0x14) */ 656/* #define CPMVEC_TIMER2 ((ushort)0x12) */ 657/* #define CPMVEC_RISCTIMER ((ushort)0x11) */ 658/* #define CPMVEC_I2C ((ushort)0x10) */ 659/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */ 660/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */ 661/* #define CPMVEC_TIMER3 ((ushort)0x0c) */ 662/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */ 663/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */ 664/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */ 665/* #define CPMVEC_TIMER4 ((ushort)0x07) */ 666/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */ 667/* #define CPMVEC_SPI ((ushort)0x05) */ 668/* #define CPMVEC_SMC1 ((ushort)0x04) */ 669/* #define CPMVEC_SMC2 ((ushort)0x03) */ 670/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */ 671/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */ 672/* #define CPMVEC_ERROR ((ushort)0x00) */ 673 674extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); 675 676/* CPM interrupt configuration vector. 677*/ 678#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 679#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 680#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 681#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 682#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ 683#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 684#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 685#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 686#endif /* __CPM_360__ */ 687