1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org) 7 */ 8#ifndef __ASM_BARRIER_H 9#define __ASM_BARRIER_H 10 11#include <asm/addrspace.h> 12 13/* 14 * read_barrier_depends - Flush all pending reads that subsequents reads 15 * depend on. 16 * 17 * No data-dependent reads from memory-like regions are ever reordered 18 * over this barrier. All reads preceding this primitive are guaranteed 19 * to access memory (but not necessarily other CPUs' caches) before any 20 * reads following this primitive that depend on the data return by 21 * any of the preceding reads. This primitive is much lighter weight than 22 * rmb() on most CPUs, and is never heavier weight than is 23 * rmb(). 24 * 25 * These ordering constraints are respected by both the local CPU 26 * and the compiler. 27 * 28 * Ordering is not guaranteed by anything other than these primitives, 29 * not even by data dependencies. See the documentation for 30 * memory_barrier() for examples and URLs to more information. 31 * 32 * For example, the following code would force ordering (the initial 33 * value of "a" is zero, "b" is one, and "p" is "&a"): 34 * 35 * <programlisting> 36 * CPU 0 CPU 1 37 * 38 * b = 2; 39 * memory_barrier(); 40 * p = &b; q = p; 41 * read_barrier_depends(); 42 * d = *q; 43 * </programlisting> 44 * 45 * because the read of "*q" depends on the read of "p" and these 46 * two reads are separated by a read_barrier_depends(). However, 47 * the following code, with the same initial values for "a" and "b": 48 * 49 * <programlisting> 50 * CPU 0 CPU 1 51 * 52 * a = 2; 53 * memory_barrier(); 54 * b = 3; y = b; 55 * read_barrier_depends(); 56 * x = a; 57 * </programlisting> 58 * 59 * does not enforce ordering, since there is no data dependency between 60 * the read of "a" and the read of "b". Therefore, on some CPUs, such 61 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() 62 * in cases like this where there are no data dependencies. 63 */ 64 65#define read_barrier_depends() do { } while(0) 66#define smp_read_barrier_depends() do { } while(0) 67 68#ifdef CONFIG_CPU_HAS_SYNC 69#define __sync() \ 70 __asm__ __volatile__( \ 71 ".set push\n\t" \ 72 ".set noreorder\n\t" \ 73 ".set mips2\n\t" \ 74 "sync\n\t" \ 75 ".set pop" \ 76 : /* no output */ \ 77 : /* no input */ \ 78 : "memory") 79#else 80#define __sync() do { } while(0) 81#endif 82 83#define __fast_iob() \ 84 __asm__ __volatile__( \ 85 ".set push\n\t" \ 86 ".set noreorder\n\t" \ 87 "lw $0,%0\n\t" \ 88 "nop\n\t" \ 89 ".set pop" \ 90 : /* no output */ \ 91 : "m" (*(int *)CKSEG1) \ 92 : "memory") 93#ifdef CONFIG_CPU_CAVIUM_OCTEON 94# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n" 95# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory") 96 97# define fast_wmb() __syncw() 98# define fast_rmb() barrier() 99# define fast_mb() __sync() 100# define fast_iob() do { } while (0) 101#else /* ! CONFIG_CPU_CAVIUM_OCTEON */ 102# define fast_wmb() __sync() 103# define fast_rmb() __sync() 104# define fast_mb() __sync() 105# ifdef CONFIG_SGI_IP28 106# define fast_iob() \ 107 __asm__ __volatile__( \ 108 ".set push\n\t" \ 109 ".set noreorder\n\t" \ 110 "lw $0,%0\n\t" \ 111 "sync\n\t" \ 112 "lw $0,%0\n\t" \ 113 ".set pop" \ 114 : /* no output */ \ 115 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ 116 : "memory") 117# else 118# define fast_iob() \ 119 do { \ 120 __sync(); \ 121 __fast_iob(); \ 122 } while (0) 123# endif 124#endif /* CONFIG_CPU_CAVIUM_OCTEON */ 125 126#ifdef CONFIG_CPU_HAS_WB 127 128#include <asm/wbflush.h> 129 130#define wmb() fast_wmb() 131#define rmb() fast_rmb() 132#define mb() wbflush() 133#define iob() wbflush() 134 135#else /* !CONFIG_CPU_HAS_WB */ 136 137#define wmb() fast_wmb() 138#define rmb() fast_rmb() 139#define mb() fast_mb() 140#define iob() fast_iob() 141 142#endif /* !CONFIG_CPU_HAS_WB */ 143 144#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) 145# ifdef CONFIG_CPU_CAVIUM_OCTEON 146# define smp_mb() __sync() 147# define smp_rmb() barrier() 148# define smp_wmb() __syncw() 149# else 150# define smp_mb() __asm__ __volatile__("sync" : : :"memory") 151# define smp_rmb() __asm__ __volatile__("sync" : : :"memory") 152# define smp_wmb() __asm__ __volatile__("sync" : : :"memory") 153# endif 154#else 155#define smp_mb() barrier() 156#define smp_rmb() barrier() 157#define smp_wmb() barrier() 158#endif 159 160#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) 161#define __WEAK_LLSC_MB " sync \n" 162#else 163#define __WEAK_LLSC_MB " \n" 164#endif 165 166#define set_mb(var, value) \ 167 do { var = value; smp_mb(); } while (0) 168 169#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 170 171#ifdef CONFIG_CPU_CAVIUM_OCTEON 172#define smp_mb__before_llsc() smp_wmb() 173/* Cause previous writes to become visible on all CPUs as soon as possible */ 174#define nudge_writes() __asm__ __volatile__(".set push\n\t" \ 175 ".set arch=octeon\n\t" \ 176 "syncw\n\t" \ 177 ".set pop" : : : "memory") 178#else 179#define smp_mb__before_llsc() smp_llsc_mb() 180#define nudge_writes() mb() 181#endif 182 183#define smp_store_release(p, v) \ 184do { \ 185 compiletime_assert_atomic_type(*p); \ 186 smp_mb(); \ 187 ACCESS_ONCE(*p) = (v); \ 188} while (0) 189 190#define smp_load_acquire(p) \ 191({ \ 192 typeof(*p) ___p1 = ACCESS_ONCE(*p); \ 193 compiletime_assert_atomic_type(*p); \ 194 smp_mb(); \ 195 ___p1; \ 196}) 197 198#define smp_mb__before_atomic() smp_mb__before_llsc() 199#define smp_mb__after_atomic() smp_llsc_mb() 200 201#endif /* __ASM_BARRIER_H */ 202