1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_ASXX_DEFS_H__ 29#define __CVMX_ASXX_DEFS_H__ 30 31#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) 32#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) 33#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) 34#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) 35#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) 36#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) 37#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) 38#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) 39#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) 40#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) 41#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) 42#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) 43#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) 44#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) 45#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) 46#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) 47#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 48#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) 49#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) 50#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) 51#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) 52#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) 53#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 54#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) 55#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 56#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) 57 58union cvmx_asxx_gmii_rx_clk_set { 59 uint64_t u64; 60 struct cvmx_asxx_gmii_rx_clk_set_s { 61#ifdef __BIG_ENDIAN_BITFIELD 62 uint64_t reserved_5_63:59; 63 uint64_t setting:5; 64#else 65 uint64_t setting:5; 66 uint64_t reserved_5_63:59; 67#endif 68 } s; 69 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; 70 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; 71 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; 72}; 73 74union cvmx_asxx_gmii_rx_dat_set { 75 uint64_t u64; 76 struct cvmx_asxx_gmii_rx_dat_set_s { 77#ifdef __BIG_ENDIAN_BITFIELD 78 uint64_t reserved_5_63:59; 79 uint64_t setting:5; 80#else 81 uint64_t setting:5; 82 uint64_t reserved_5_63:59; 83#endif 84 } s; 85 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; 86 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; 87 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; 88}; 89 90union cvmx_asxx_int_en { 91 uint64_t u64; 92 struct cvmx_asxx_int_en_s { 93#ifdef __BIG_ENDIAN_BITFIELD 94 uint64_t reserved_12_63:52; 95 uint64_t txpsh:4; 96 uint64_t txpop:4; 97 uint64_t ovrflw:4; 98#else 99 uint64_t ovrflw:4; 100 uint64_t txpop:4; 101 uint64_t txpsh:4; 102 uint64_t reserved_12_63:52; 103#endif 104 } s; 105 struct cvmx_asxx_int_en_cn30xx { 106#ifdef __BIG_ENDIAN_BITFIELD 107 uint64_t reserved_11_63:53; 108 uint64_t txpsh:3; 109 uint64_t reserved_7_7:1; 110 uint64_t txpop:3; 111 uint64_t reserved_3_3:1; 112 uint64_t ovrflw:3; 113#else 114 uint64_t ovrflw:3; 115 uint64_t reserved_3_3:1; 116 uint64_t txpop:3; 117 uint64_t reserved_7_7:1; 118 uint64_t txpsh:3; 119 uint64_t reserved_11_63:53; 120#endif 121 } cn30xx; 122 struct cvmx_asxx_int_en_cn30xx cn31xx; 123 struct cvmx_asxx_int_en_s cn38xx; 124 struct cvmx_asxx_int_en_s cn38xxp2; 125 struct cvmx_asxx_int_en_cn30xx cn50xx; 126 struct cvmx_asxx_int_en_s cn58xx; 127 struct cvmx_asxx_int_en_s cn58xxp1; 128}; 129 130union cvmx_asxx_int_reg { 131 uint64_t u64; 132 struct cvmx_asxx_int_reg_s { 133#ifdef __BIG_ENDIAN_BITFIELD 134 uint64_t reserved_12_63:52; 135 uint64_t txpsh:4; 136 uint64_t txpop:4; 137 uint64_t ovrflw:4; 138#else 139 uint64_t ovrflw:4; 140 uint64_t txpop:4; 141 uint64_t txpsh:4; 142 uint64_t reserved_12_63:52; 143#endif 144 } s; 145 struct cvmx_asxx_int_reg_cn30xx { 146#ifdef __BIG_ENDIAN_BITFIELD 147 uint64_t reserved_11_63:53; 148 uint64_t txpsh:3; 149 uint64_t reserved_7_7:1; 150 uint64_t txpop:3; 151 uint64_t reserved_3_3:1; 152 uint64_t ovrflw:3; 153#else 154 uint64_t ovrflw:3; 155 uint64_t reserved_3_3:1; 156 uint64_t txpop:3; 157 uint64_t reserved_7_7:1; 158 uint64_t txpsh:3; 159 uint64_t reserved_11_63:53; 160#endif 161 } cn30xx; 162 struct cvmx_asxx_int_reg_cn30xx cn31xx; 163 struct cvmx_asxx_int_reg_s cn38xx; 164 struct cvmx_asxx_int_reg_s cn38xxp2; 165 struct cvmx_asxx_int_reg_cn30xx cn50xx; 166 struct cvmx_asxx_int_reg_s cn58xx; 167 struct cvmx_asxx_int_reg_s cn58xxp1; 168}; 169 170union cvmx_asxx_mii_rx_dat_set { 171 uint64_t u64; 172 struct cvmx_asxx_mii_rx_dat_set_s { 173#ifdef __BIG_ENDIAN_BITFIELD 174 uint64_t reserved_5_63:59; 175 uint64_t setting:5; 176#else 177 uint64_t setting:5; 178 uint64_t reserved_5_63:59; 179#endif 180 } s; 181 struct cvmx_asxx_mii_rx_dat_set_s cn30xx; 182 struct cvmx_asxx_mii_rx_dat_set_s cn50xx; 183}; 184 185union cvmx_asxx_prt_loop { 186 uint64_t u64; 187 struct cvmx_asxx_prt_loop_s { 188#ifdef __BIG_ENDIAN_BITFIELD 189 uint64_t reserved_8_63:56; 190 uint64_t ext_loop:4; 191 uint64_t int_loop:4; 192#else 193 uint64_t int_loop:4; 194 uint64_t ext_loop:4; 195 uint64_t reserved_8_63:56; 196#endif 197 } s; 198 struct cvmx_asxx_prt_loop_cn30xx { 199#ifdef __BIG_ENDIAN_BITFIELD 200 uint64_t reserved_7_63:57; 201 uint64_t ext_loop:3; 202 uint64_t reserved_3_3:1; 203 uint64_t int_loop:3; 204#else 205 uint64_t int_loop:3; 206 uint64_t reserved_3_3:1; 207 uint64_t ext_loop:3; 208 uint64_t reserved_7_63:57; 209#endif 210 } cn30xx; 211 struct cvmx_asxx_prt_loop_cn30xx cn31xx; 212 struct cvmx_asxx_prt_loop_s cn38xx; 213 struct cvmx_asxx_prt_loop_s cn38xxp2; 214 struct cvmx_asxx_prt_loop_cn30xx cn50xx; 215 struct cvmx_asxx_prt_loop_s cn58xx; 216 struct cvmx_asxx_prt_loop_s cn58xxp1; 217}; 218 219union cvmx_asxx_rld_bypass { 220 uint64_t u64; 221 struct cvmx_asxx_rld_bypass_s { 222#ifdef __BIG_ENDIAN_BITFIELD 223 uint64_t reserved_1_63:63; 224 uint64_t bypass:1; 225#else 226 uint64_t bypass:1; 227 uint64_t reserved_1_63:63; 228#endif 229 } s; 230 struct cvmx_asxx_rld_bypass_s cn38xx; 231 struct cvmx_asxx_rld_bypass_s cn38xxp2; 232 struct cvmx_asxx_rld_bypass_s cn58xx; 233 struct cvmx_asxx_rld_bypass_s cn58xxp1; 234}; 235 236union cvmx_asxx_rld_bypass_setting { 237 uint64_t u64; 238 struct cvmx_asxx_rld_bypass_setting_s { 239#ifdef __BIG_ENDIAN_BITFIELD 240 uint64_t reserved_5_63:59; 241 uint64_t setting:5; 242#else 243 uint64_t setting:5; 244 uint64_t reserved_5_63:59; 245#endif 246 } s; 247 struct cvmx_asxx_rld_bypass_setting_s cn38xx; 248 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; 249 struct cvmx_asxx_rld_bypass_setting_s cn58xx; 250 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; 251}; 252 253union cvmx_asxx_rld_comp { 254 uint64_t u64; 255 struct cvmx_asxx_rld_comp_s { 256#ifdef __BIG_ENDIAN_BITFIELD 257 uint64_t reserved_9_63:55; 258 uint64_t pctl:5; 259 uint64_t nctl:4; 260#else 261 uint64_t nctl:4; 262 uint64_t pctl:5; 263 uint64_t reserved_9_63:55; 264#endif 265 } s; 266 struct cvmx_asxx_rld_comp_cn38xx { 267#ifdef __BIG_ENDIAN_BITFIELD 268 uint64_t reserved_8_63:56; 269 uint64_t pctl:4; 270 uint64_t nctl:4; 271#else 272 uint64_t nctl:4; 273 uint64_t pctl:4; 274 uint64_t reserved_8_63:56; 275#endif 276 } cn38xx; 277 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; 278 struct cvmx_asxx_rld_comp_s cn58xx; 279 struct cvmx_asxx_rld_comp_s cn58xxp1; 280}; 281 282union cvmx_asxx_rld_data_drv { 283 uint64_t u64; 284 struct cvmx_asxx_rld_data_drv_s { 285#ifdef __BIG_ENDIAN_BITFIELD 286 uint64_t reserved_8_63:56; 287 uint64_t pctl:4; 288 uint64_t nctl:4; 289#else 290 uint64_t nctl:4; 291 uint64_t pctl:4; 292 uint64_t reserved_8_63:56; 293#endif 294 } s; 295 struct cvmx_asxx_rld_data_drv_s cn38xx; 296 struct cvmx_asxx_rld_data_drv_s cn38xxp2; 297 struct cvmx_asxx_rld_data_drv_s cn58xx; 298 struct cvmx_asxx_rld_data_drv_s cn58xxp1; 299}; 300 301union cvmx_asxx_rld_fcram_mode { 302 uint64_t u64; 303 struct cvmx_asxx_rld_fcram_mode_s { 304#ifdef __BIG_ENDIAN_BITFIELD 305 uint64_t reserved_1_63:63; 306 uint64_t mode:1; 307#else 308 uint64_t mode:1; 309 uint64_t reserved_1_63:63; 310#endif 311 } s; 312 struct cvmx_asxx_rld_fcram_mode_s cn38xx; 313 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; 314}; 315 316union cvmx_asxx_rld_nctl_strong { 317 uint64_t u64; 318 struct cvmx_asxx_rld_nctl_strong_s { 319#ifdef __BIG_ENDIAN_BITFIELD 320 uint64_t reserved_5_63:59; 321 uint64_t nctl:5; 322#else 323 uint64_t nctl:5; 324 uint64_t reserved_5_63:59; 325#endif 326 } s; 327 struct cvmx_asxx_rld_nctl_strong_s cn38xx; 328 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; 329 struct cvmx_asxx_rld_nctl_strong_s cn58xx; 330 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; 331}; 332 333union cvmx_asxx_rld_nctl_weak { 334 uint64_t u64; 335 struct cvmx_asxx_rld_nctl_weak_s { 336#ifdef __BIG_ENDIAN_BITFIELD 337 uint64_t reserved_5_63:59; 338 uint64_t nctl:5; 339#else 340 uint64_t nctl:5; 341 uint64_t reserved_5_63:59; 342#endif 343 } s; 344 struct cvmx_asxx_rld_nctl_weak_s cn38xx; 345 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; 346 struct cvmx_asxx_rld_nctl_weak_s cn58xx; 347 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; 348}; 349 350union cvmx_asxx_rld_pctl_strong { 351 uint64_t u64; 352 struct cvmx_asxx_rld_pctl_strong_s { 353#ifdef __BIG_ENDIAN_BITFIELD 354 uint64_t reserved_5_63:59; 355 uint64_t pctl:5; 356#else 357 uint64_t pctl:5; 358 uint64_t reserved_5_63:59; 359#endif 360 } s; 361 struct cvmx_asxx_rld_pctl_strong_s cn38xx; 362 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; 363 struct cvmx_asxx_rld_pctl_strong_s cn58xx; 364 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; 365}; 366 367union cvmx_asxx_rld_pctl_weak { 368 uint64_t u64; 369 struct cvmx_asxx_rld_pctl_weak_s { 370#ifdef __BIG_ENDIAN_BITFIELD 371 uint64_t reserved_5_63:59; 372 uint64_t pctl:5; 373#else 374 uint64_t pctl:5; 375 uint64_t reserved_5_63:59; 376#endif 377 } s; 378 struct cvmx_asxx_rld_pctl_weak_s cn38xx; 379 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; 380 struct cvmx_asxx_rld_pctl_weak_s cn58xx; 381 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; 382}; 383 384union cvmx_asxx_rld_setting { 385 uint64_t u64; 386 struct cvmx_asxx_rld_setting_s { 387#ifdef __BIG_ENDIAN_BITFIELD 388 uint64_t reserved_13_63:51; 389 uint64_t dfaset:5; 390 uint64_t dfalag:1; 391 uint64_t dfalead:1; 392 uint64_t dfalock:1; 393 uint64_t setting:5; 394#else 395 uint64_t setting:5; 396 uint64_t dfalock:1; 397 uint64_t dfalead:1; 398 uint64_t dfalag:1; 399 uint64_t dfaset:5; 400 uint64_t reserved_13_63:51; 401#endif 402 } s; 403 struct cvmx_asxx_rld_setting_cn38xx { 404#ifdef __BIG_ENDIAN_BITFIELD 405 uint64_t reserved_5_63:59; 406 uint64_t setting:5; 407#else 408 uint64_t setting:5; 409 uint64_t reserved_5_63:59; 410#endif 411 } cn38xx; 412 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; 413 struct cvmx_asxx_rld_setting_s cn58xx; 414 struct cvmx_asxx_rld_setting_s cn58xxp1; 415}; 416 417union cvmx_asxx_rx_clk_setx { 418 uint64_t u64; 419 struct cvmx_asxx_rx_clk_setx_s { 420#ifdef __BIG_ENDIAN_BITFIELD 421 uint64_t reserved_5_63:59; 422 uint64_t setting:5; 423#else 424 uint64_t setting:5; 425 uint64_t reserved_5_63:59; 426#endif 427 } s; 428 struct cvmx_asxx_rx_clk_setx_s cn30xx; 429 struct cvmx_asxx_rx_clk_setx_s cn31xx; 430 struct cvmx_asxx_rx_clk_setx_s cn38xx; 431 struct cvmx_asxx_rx_clk_setx_s cn38xxp2; 432 struct cvmx_asxx_rx_clk_setx_s cn50xx; 433 struct cvmx_asxx_rx_clk_setx_s cn58xx; 434 struct cvmx_asxx_rx_clk_setx_s cn58xxp1; 435}; 436 437union cvmx_asxx_rx_prt_en { 438 uint64_t u64; 439 struct cvmx_asxx_rx_prt_en_s { 440#ifdef __BIG_ENDIAN_BITFIELD 441 uint64_t reserved_4_63:60; 442 uint64_t prt_en:4; 443#else 444 uint64_t prt_en:4; 445 uint64_t reserved_4_63:60; 446#endif 447 } s; 448 struct cvmx_asxx_rx_prt_en_cn30xx { 449#ifdef __BIG_ENDIAN_BITFIELD 450 uint64_t reserved_3_63:61; 451 uint64_t prt_en:3; 452#else 453 uint64_t prt_en:3; 454 uint64_t reserved_3_63:61; 455#endif 456 } cn30xx; 457 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; 458 struct cvmx_asxx_rx_prt_en_s cn38xx; 459 struct cvmx_asxx_rx_prt_en_s cn38xxp2; 460 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; 461 struct cvmx_asxx_rx_prt_en_s cn58xx; 462 struct cvmx_asxx_rx_prt_en_s cn58xxp1; 463}; 464 465union cvmx_asxx_rx_wol { 466 uint64_t u64; 467 struct cvmx_asxx_rx_wol_s { 468#ifdef __BIG_ENDIAN_BITFIELD 469 uint64_t reserved_2_63:62; 470 uint64_t status:1; 471 uint64_t enable:1; 472#else 473 uint64_t enable:1; 474 uint64_t status:1; 475 uint64_t reserved_2_63:62; 476#endif 477 } s; 478 struct cvmx_asxx_rx_wol_s cn38xx; 479 struct cvmx_asxx_rx_wol_s cn38xxp2; 480}; 481 482union cvmx_asxx_rx_wol_msk { 483 uint64_t u64; 484 struct cvmx_asxx_rx_wol_msk_s { 485#ifdef __BIG_ENDIAN_BITFIELD 486 uint64_t msk:64; 487#else 488 uint64_t msk:64; 489#endif 490 } s; 491 struct cvmx_asxx_rx_wol_msk_s cn38xx; 492 struct cvmx_asxx_rx_wol_msk_s cn38xxp2; 493}; 494 495union cvmx_asxx_rx_wol_powok { 496 uint64_t u64; 497 struct cvmx_asxx_rx_wol_powok_s { 498#ifdef __BIG_ENDIAN_BITFIELD 499 uint64_t reserved_1_63:63; 500 uint64_t powerok:1; 501#else 502 uint64_t powerok:1; 503 uint64_t reserved_1_63:63; 504#endif 505 } s; 506 struct cvmx_asxx_rx_wol_powok_s cn38xx; 507 struct cvmx_asxx_rx_wol_powok_s cn38xxp2; 508}; 509 510union cvmx_asxx_rx_wol_sig { 511 uint64_t u64; 512 struct cvmx_asxx_rx_wol_sig_s { 513#ifdef __BIG_ENDIAN_BITFIELD 514 uint64_t reserved_32_63:32; 515 uint64_t sig:32; 516#else 517 uint64_t sig:32; 518 uint64_t reserved_32_63:32; 519#endif 520 } s; 521 struct cvmx_asxx_rx_wol_sig_s cn38xx; 522 struct cvmx_asxx_rx_wol_sig_s cn38xxp2; 523}; 524 525union cvmx_asxx_tx_clk_setx { 526 uint64_t u64; 527 struct cvmx_asxx_tx_clk_setx_s { 528#ifdef __BIG_ENDIAN_BITFIELD 529 uint64_t reserved_5_63:59; 530 uint64_t setting:5; 531#else 532 uint64_t setting:5; 533 uint64_t reserved_5_63:59; 534#endif 535 } s; 536 struct cvmx_asxx_tx_clk_setx_s cn30xx; 537 struct cvmx_asxx_tx_clk_setx_s cn31xx; 538 struct cvmx_asxx_tx_clk_setx_s cn38xx; 539 struct cvmx_asxx_tx_clk_setx_s cn38xxp2; 540 struct cvmx_asxx_tx_clk_setx_s cn50xx; 541 struct cvmx_asxx_tx_clk_setx_s cn58xx; 542 struct cvmx_asxx_tx_clk_setx_s cn58xxp1; 543}; 544 545union cvmx_asxx_tx_comp_byp { 546 uint64_t u64; 547 struct cvmx_asxx_tx_comp_byp_s { 548#ifdef __BIG_ENDIAN_BITFIELD 549 uint64_t reserved_0_63:64; 550#else 551 uint64_t reserved_0_63:64; 552#endif 553 } s; 554 struct cvmx_asxx_tx_comp_byp_cn30xx { 555#ifdef __BIG_ENDIAN_BITFIELD 556 uint64_t reserved_9_63:55; 557 uint64_t bypass:1; 558 uint64_t pctl:4; 559 uint64_t nctl:4; 560#else 561 uint64_t nctl:4; 562 uint64_t pctl:4; 563 uint64_t bypass:1; 564 uint64_t reserved_9_63:55; 565#endif 566 } cn30xx; 567 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; 568 struct cvmx_asxx_tx_comp_byp_cn38xx { 569#ifdef __BIG_ENDIAN_BITFIELD 570 uint64_t reserved_8_63:56; 571 uint64_t pctl:4; 572 uint64_t nctl:4; 573#else 574 uint64_t nctl:4; 575 uint64_t pctl:4; 576 uint64_t reserved_8_63:56; 577#endif 578 } cn38xx; 579 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; 580 struct cvmx_asxx_tx_comp_byp_cn50xx { 581#ifdef __BIG_ENDIAN_BITFIELD 582 uint64_t reserved_17_63:47; 583 uint64_t bypass:1; 584 uint64_t reserved_13_15:3; 585 uint64_t pctl:5; 586 uint64_t reserved_5_7:3; 587 uint64_t nctl:5; 588#else 589 uint64_t nctl:5; 590 uint64_t reserved_5_7:3; 591 uint64_t pctl:5; 592 uint64_t reserved_13_15:3; 593 uint64_t bypass:1; 594 uint64_t reserved_17_63:47; 595#endif 596 } cn50xx; 597 struct cvmx_asxx_tx_comp_byp_cn58xx { 598#ifdef __BIG_ENDIAN_BITFIELD 599 uint64_t reserved_13_63:51; 600 uint64_t pctl:5; 601 uint64_t reserved_5_7:3; 602 uint64_t nctl:5; 603#else 604 uint64_t nctl:5; 605 uint64_t reserved_5_7:3; 606 uint64_t pctl:5; 607 uint64_t reserved_13_63:51; 608#endif 609 } cn58xx; 610 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; 611}; 612 613union cvmx_asxx_tx_hi_waterx { 614 uint64_t u64; 615 struct cvmx_asxx_tx_hi_waterx_s { 616#ifdef __BIG_ENDIAN_BITFIELD 617 uint64_t reserved_4_63:60; 618 uint64_t mark:4; 619#else 620 uint64_t mark:4; 621 uint64_t reserved_4_63:60; 622#endif 623 } s; 624 struct cvmx_asxx_tx_hi_waterx_cn30xx { 625#ifdef __BIG_ENDIAN_BITFIELD 626 uint64_t reserved_3_63:61; 627 uint64_t mark:3; 628#else 629 uint64_t mark:3; 630 uint64_t reserved_3_63:61; 631#endif 632 } cn30xx; 633 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; 634 struct cvmx_asxx_tx_hi_waterx_s cn38xx; 635 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; 636 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; 637 struct cvmx_asxx_tx_hi_waterx_s cn58xx; 638 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; 639}; 640 641union cvmx_asxx_tx_prt_en { 642 uint64_t u64; 643 struct cvmx_asxx_tx_prt_en_s { 644#ifdef __BIG_ENDIAN_BITFIELD 645 uint64_t reserved_4_63:60; 646 uint64_t prt_en:4; 647#else 648 uint64_t prt_en:4; 649 uint64_t reserved_4_63:60; 650#endif 651 } s; 652 struct cvmx_asxx_tx_prt_en_cn30xx { 653#ifdef __BIG_ENDIAN_BITFIELD 654 uint64_t reserved_3_63:61; 655 uint64_t prt_en:3; 656#else 657 uint64_t prt_en:3; 658 uint64_t reserved_3_63:61; 659#endif 660 } cn30xx; 661 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; 662 struct cvmx_asxx_tx_prt_en_s cn38xx; 663 struct cvmx_asxx_tx_prt_en_s cn38xxp2; 664 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; 665 struct cvmx_asxx_tx_prt_en_s cn58xx; 666 struct cvmx_asxx_tx_prt_en_s cn58xxp1; 667}; 668 669#endif 670