1/*
2 *  This program is free software; you can redistribute it and/or modify it
3 *  under the terms of the GNU General Public License version 2 as published
4 *  by the Free Software Foundation.
5 *
6 *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/vmalloc.h>
16#include <linux/module.h>
17#include <linux/clk.h>
18#include <linux/of_platform.h>
19#include <linux/of_gpio.h>
20#include <linux/of_irq.h>
21#include <linux/of_pci.h>
22
23#include <asm/pci.h>
24#include <asm/gpio.h>
25#include <asm/addrspace.h>
26
27#include <lantiq_soc.h>
28#include <lantiq_irq.h>
29
30#include "pci-lantiq.h"
31
32#define PCI_CR_FCI_ADDR_MAP0		0x00C0
33#define PCI_CR_FCI_ADDR_MAP1		0x00C4
34#define PCI_CR_FCI_ADDR_MAP2		0x00C8
35#define PCI_CR_FCI_ADDR_MAP3		0x00CC
36#define PCI_CR_FCI_ADDR_MAP4		0x00D0
37#define PCI_CR_FCI_ADDR_MAP5		0x00D4
38#define PCI_CR_FCI_ADDR_MAP6		0x00D8
39#define PCI_CR_FCI_ADDR_MAP7		0x00DC
40#define PCI_CR_CLK_CTRL			0x0000
41#define PCI_CR_PCI_MOD			0x0030
42#define PCI_CR_PC_ARB			0x0080
43#define PCI_CR_FCI_ADDR_MAP11hg		0x00E4
44#define PCI_CR_BAR11MASK		0x0044
45#define PCI_CR_BAR12MASK		0x0048
46#define PCI_CR_BAR13MASK		0x004C
47#define PCI_CS_BASE_ADDR1		0x0010
48#define PCI_CR_PCI_ADDR_MAP11		0x0064
49#define PCI_CR_FCI_BURST_LENGTH		0x00E8
50#define PCI_CR_PCI_EOI			0x002C
51#define PCI_CS_STS_CMD			0x0004
52
53#define PCI_MASTER0_REQ_MASK_2BITS	8
54#define PCI_MASTER1_REQ_MASK_2BITS	10
55#define PCI_MASTER2_REQ_MASK_2BITS	12
56#define INTERNAL_ARB_ENABLE_BIT		0
57
58#define LTQ_CGU_IFCCR		0x0018
59#define LTQ_CGU_PCICR		0x0034
60
61#define ltq_pci_w32(x, y)	ltq_w32((x), ltq_pci_membase + (y))
62#define ltq_pci_r32(x)		ltq_r32(ltq_pci_membase + (x))
63
64#define ltq_pci_cfg_w32(x, y)	ltq_w32((x), ltq_pci_mapped_cfg + (y))
65#define ltq_pci_cfg_r32(x)	ltq_r32(ltq_pci_mapped_cfg + (x))
66
67__iomem void *ltq_pci_mapped_cfg;
68static __iomem void *ltq_pci_membase;
69
70static int reset_gpio;
71static struct clk *clk_pci, *clk_external;
72static struct resource pci_io_resource;
73static struct resource pci_mem_resource;
74static struct pci_ops pci_ops = {
75	.read	= ltq_pci_read_config_dword,
76	.write	= ltq_pci_write_config_dword
77};
78
79static struct pci_controller pci_controller = {
80	.pci_ops	= &pci_ops,
81	.mem_resource	= &pci_mem_resource,
82	.mem_offset	= 0x00000000UL,
83	.io_resource	= &pci_io_resource,
84	.io_offset	= 0x00000000UL,
85};
86
87static inline u32 ltq_calc_bar11mask(void)
88{
89	u32 mem, bar11mask;
90
91	/* BAR11MASK value depends on available memory on system. */
92	mem = get_num_physpages() * PAGE_SIZE;
93	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
94
95	return bar11mask;
96}
97
98static int ltq_pci_startup(struct platform_device *pdev)
99{
100	struct device_node *node = pdev->dev.of_node;
101	const __be32 *req_mask, *bus_clk;
102	u32 temp_buffer;
103
104	/* get our clocks */
105	clk_pci = clk_get(&pdev->dev, NULL);
106	if (IS_ERR(clk_pci)) {
107		dev_err(&pdev->dev, "failed to get pci clock\n");
108		return PTR_ERR(clk_pci);
109	}
110
111	clk_external = clk_get(&pdev->dev, "external");
112	if (IS_ERR(clk_external)) {
113		clk_put(clk_pci);
114		dev_err(&pdev->dev, "failed to get external pci clock\n");
115		return PTR_ERR(clk_external);
116	}
117
118	/* read the bus speed that we want */
119	bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
120	if (bus_clk)
121		clk_set_rate(clk_pci, *bus_clk);
122
123	/* and enable the clocks */
124	clk_enable(clk_pci);
125	if (of_find_property(node, "lantiq,external-clock", NULL))
126		clk_enable(clk_external);
127	else
128		clk_disable(clk_external);
129
130	/* setup reset gpio used by pci */
131	reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
132	if (gpio_is_valid(reset_gpio)) {
133		int ret = devm_gpio_request(&pdev->dev,
134						reset_gpio, "pci-reset");
135		if (ret) {
136			dev_err(&pdev->dev,
137				"failed to request gpio %d\n", reset_gpio);
138			return ret;
139		}
140		gpio_direction_output(reset_gpio, 1);
141	}
142
143	/* enable auto-switching between PCI and EBU */
144	ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
145
146	/* busy, i.e. configuration is not done, PCI access has to be retried */
147	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
148	wmb();
149	/* BUS Master/IO/MEM access */
150	ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
151
152	/* enable external 2 PCI masters */
153	temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
154	/* setup the request mask */
155	req_mask = of_get_property(node, "req-mask", NULL);
156	if (req_mask)
157		temp_buffer &= ~((*req_mask & 0xf) << 16);
158	else
159		temp_buffer &= ~0xf0000;
160	/* enable internal arbiter */
161	temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
162	/* enable internal PCI master reqest */
163	temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
164
165	/* enable EBU request */
166	temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
167
168	/* enable all external masters request */
169	temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
170	ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
171	wmb();
172
173	/* setup BAR memory regions */
174	ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
175	ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
176	ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
177	ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
178	ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
179	ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
180	ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
181	ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
182	ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
183	ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
184	ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
185	ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
186	/* both TX and RX endian swap are enabled */
187	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
188	wmb();
189	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
190		PCI_CR_BAR12MASK);
191	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
192		PCI_CR_BAR13MASK);
193	/*use 8 dw burst length */
194	ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
195	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
196	wmb();
197
198	/* setup irq line */
199	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
200	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
201
202	/* toggle reset pin */
203	if (gpio_is_valid(reset_gpio)) {
204		__gpio_set_value(reset_gpio, 0);
205		wmb();
206		mdelay(1);
207		__gpio_set_value(reset_gpio, 1);
208	}
209	return 0;
210}
211
212static int ltq_pci_probe(struct platform_device *pdev)
213{
214	struct resource *res_cfg, *res_bridge;
215
216	pci_clear_flags(PCI_PROBE_ONLY);
217
218	res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
219	ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
220	if (IS_ERR(ltq_pci_membase))
221		return PTR_ERR(ltq_pci_membase);
222
223	res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224	ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
225	if (IS_ERR(ltq_pci_mapped_cfg))
226		return PTR_ERR(ltq_pci_mapped_cfg);
227
228	ltq_pci_startup(pdev);
229
230	pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
231	register_pci_controller(&pci_controller);
232	return 0;
233}
234
235static const struct of_device_id ltq_pci_match[] = {
236	{ .compatible = "lantiq,pci-xway" },
237	{},
238};
239MODULE_DEVICE_TABLE(of, ltq_pci_match);
240
241static struct platform_driver ltq_pci_driver = {
242	.probe = ltq_pci_probe,
243	.driver = {
244		.name = "pci-xway",
245		.owner = THIS_MODULE,
246		.of_match_table = ltq_pci_match,
247	},
248};
249
250int __init pcibios_init(void)
251{
252	int ret = platform_driver_register(&ltq_pci_driver);
253	if (ret)
254		pr_info("pci-xway: Error registering platform driver!");
255	return ret;
256}
257
258arch_initcall(pcibios_init);
259